Timeline for Why are the outputs of these gates tied together in the Apollo Guidance Computer?
Current License: CC BY-SA 4.0
15 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 17, 2021 at 16:39 | comment | added | stix | @WhatRoughBeast So you're saying it's an OR gate, hack is saying it's a NOR gate... Who's right? And TTL chips are still being sold today, RTL chips notsomuch. So it's still "modern." Yes, I'm aware I could use CMOS gates instead but 74LS** chips are cheap and plentiful. | |
| May 16, 2021 at 13:24 | comment | added | WhatRoughBeast | @stix - "So if I were to draw this schematic in modern TTL instead, I could replace those wire tie points with an extra NOR gate? " Well, first off, TTL is not remotely "modern" any more. More to the point, you COULD replace those with an extra OR gate, not a NOR. Or, just for fun, if you invert your inputs, you can replace your first level of NOR gates with AND gates (DeMorgan's Theorem). There are several TTL AND gates with open-collector outputs, such as the 7409 and 7415. Using these you can tie the outputs together, although you'll need an external pullup resistor. | |
| May 13, 2021 at 17:46 | vote | accept | stix | ||
| May 11, 2021 at 15:58 | comment | added | Circuit fantasist | @stix, Note that the input signals (voltages) are inverted by the transistors so that when only one of the input voltages is high, the "resistance" (between the collector and emitter) of the corresponding transistor is zero; so the output voltage is zero. Only when both input voltages are low, both transistors are off; so their collector-emitter "resistances" are infinite (open circiit) and the output voltage is high. | |
| May 11, 2021 at 15:15 | history | edited | hacktastical | CC BY-SA 4.0 |
deleted 1 character in body
|
| May 11, 2021 at 4:21 | history | edited | hacktastical | CC BY-SA 4.0 |
added 15 characters in body
|
| May 10, 2021 at 21:42 | comment | added | hacktastical | Not sure what you're saying here. When all the tied-gate inputs are low, none of the NPN transistors are ON. Then the output is pulled up by the resistor. If any one of the inputs is high, its NPN will pull the line low. | |
| May 10, 2021 at 21:37 | comment | added | stix | If it's a wire NOR gate though, shouldn't the tied wire be logic high if both gates' outputs are low? How does it get high then if both drivers are low? | |
| May 10, 2021 at 20:01 | comment | added | hacktastical | Yes, you'd add a gate. Or you could use diodes to 'or' them, a technique I've used for reset circuits. | |
| May 10, 2021 at 19:58 | comment | added | stix | So if I were to draw this schematic in modern TTL instead, I could replace those wire tie points with an extra NOR gate? | |
| May 10, 2021 at 19:44 | history | edited | hacktastical | CC BY-SA 4.0 |
added 62 characters in body
|
| May 10, 2021 at 19:39 | history | edited | hacktastical | CC BY-SA 4.0 |
added 62 characters in body
|
| May 10, 2021 at 19:31 | history | edited | hacktastical | CC BY-SA 4.0 |
added 62 characters in body
|
| May 10, 2021 at 19:25 | history | edited | hacktastical | CC BY-SA 4.0 |
added 62 characters in body
|
| May 10, 2021 at 19:16 | history | answered | hacktastical | CC BY-SA 4.0 |