Timeline for Problem of metastability: simulation of dual port ram
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
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| Jun 21, 2021 at 8:10 | comment | added | Mitu Raj | You have already accepted an answer and the edit has changed the question's nature. You should better be asking it as separate question. | |
| Jun 21, 2021 at 8:01 | history | edited | LeeLeeYa | CC BY-SA 4.0 |
added 591 characters in body
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| Jun 21, 2021 at 7:36 | vote | accept | LeeLeeYa | ||
| Jun 21, 2021 at 7:35 | vote | accept | LeeLeeYa | ||
| Jun 21, 2021 at 7:36 | |||||
| Jun 21, 2021 at 7:16 | comment | added | LeeLeeYa |
@MituRaj Smth like this : if(rising_edge(clk_main)) then , the next line if(rising_edge(clk_a)) then .... Do I need main clk ( system clk)?
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| Jun 21, 2021 at 7:12 | comment | added | Mitu Raj | Not at all necessary. You can use two synchronous clocks of different/same frequencies on both sides. And in that way there is no metastability concerns. Block rams are designed for synchronous operations only. However Xilinx has mentioned a work around in their Bram doc if you really want asynchronous clocking. | |
| Jun 21, 2021 at 7:10 | comment | added | Mitu Raj | I am afraid that's on data lines of SPI or I2C not a clock line. Your interpretation is wrong. You simply can't do what you did here. | |
| Jun 21, 2021 at 6:45 | answer | added | Neil_UK | timeline score: 2 | |
| Jun 21, 2021 at 6:39 | comment | added | LeeLeeYa | @MituRaj Could Dual port ram be implemented with one clock? is it important to have different clk for ports? | |
| Jun 21, 2021 at 6:37 | comment | added | LeeLeeYa | @MituRaj I have found it as an example for solving metastability problem...it was done for SPI and I2C in the similar way | |
| Jun 21, 2021 at 6:33 | comment | added | Mitu Raj | The whole clk crossing process is an example for bad coding practice. | |
| Jun 21, 2021 at 6:31 | comment | added | LeeLeeYa | @MituRaj process(a_clk_bb )? | |
| Jun 21, 2021 at 6:23 | comment | added | Mitu Raj | You never should put any user logic on clock path like that, especially on FPGAs. It's mentioned in Xilinx synthesis guide. | |
| Jun 21, 2021 at 5:58 | history | asked | LeeLeeYa | CC BY-SA 4.0 |