i simulate Dual Port Ram Register in VHDL and have some doubts about the metastability problem.
Dual Port Ram has 2 clock signal, one for Port A , the second for Port B. In my simulation I create two processes with 2 differentes clocks.
type memory_type is array(0 to adress_width) of std_logic_vector(data_width-1 downto 0); --> memory array signal memory_sgnl : memory_type := (others => (others => '0'));; begin -- Port A process(clk_a) begin if(rising_edge(clk)) then if(rising_edge(clk_a)) then if(we_a = '1') then memory_sgnl (addr_a) := data_in; end if; data_out<= memory_sgnl (addr_a); end if; end process; -- Port B process(clk_b) begin if(rising_edge(clk)) then if(rising_edge(clk_b)) then if(we_b = '1') then memory_sgnl (addr_b) := data_in; end if; data_out<= memory_sgnl (addr_b); end if; end process;
I have found a post here. Mr Jim Lewis made a suggestion how DP Ram with 2 clocks can be simulated. He did the same implementation. So i can conclude I did correctly.
BUT I have read We need to solve a problem metastability, because there 2 clock signal : clock time crossing.
clk_crossing: process(clk, rst) begin if rst ='1' then -- a_clk_b <= '1'; a_clk_bb <= '1'; b_clk_b <= '1'; b_clk_bb <= '1'; elsif rising_edge(clk) then a_clk_b <= a_clk; a_clk_bb <= a_clk_b; b_clk_b <= b_clk; b_clk_bb <= b_clk_b; end if; -- if rst ='1' then end process clk_crossing;
and then the processes should be
process(a_clk_bb ) and
Will be it correct? Did I understand correctly how to solve metastability question?
The simulation of RAM is a "part" of SPI slave. SPI slave will send 8 bits vector data to RAM ( buffer of data). It has only one system clock and SPI clock + write_enb_signal ( FIFO is full and is ready to send data to RAM) . I thought Dual port RAm will work with system clk and write_enb_signal.
process(clk_a) begin if(rising_edge(clk)) then if(rising_edge(clk_a)) then ...
in the simulation spi slave there is no additional clk signal for clk_a or clk_b...
Should I create one?