Timeline for Parametric bit-width assignment in Verilog
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 23, 2023 at 15:01 | history | edited | toolic |
edited tags
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| Feb 14, 2022 at 22:59 | history | became hot network question | |||
| Feb 14, 2022 at 22:43 | answer | added | dave_59 | timeline score: 4 | |
| S Feb 14, 2022 at 13:21 | history | suggested | toolic | CC BY-SA 4.0 |
Fixed typo and grammar.
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| Feb 14, 2022 at 13:03 | review | Suggested edits | |||
| S Feb 14, 2022 at 13:21 | |||||
| Feb 14, 2022 at 12:29 | vote | accept | Jorge Johanny Sáenz Noval | ||
| Feb 14, 2022 at 11:57 | answer | added | toolic | timeline score: 5 | |
| Feb 14, 2022 at 11:40 | history | asked | Jorge Johanny Sáenz Noval | CC BY-SA 4.0 |