Skip to main content
Electrical Engineering

Return to Question

Update removed, as the underlying circuit has been modified and doesn't make any sense now to ask these questions without presenting the earlier circuit.
Source Link
Daniel
Daniel
  • 1k
  • 13
  • 24

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET. It had a flyback diode between drain and source (which is not illustrated here.)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output.)

Unluckily, BT1 is providing negative voltage when it is turned off (-3V.)

I came across with this circuit by TI:

enter image description here

I have some question about this, and I couldn't really find answers:

  1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
  2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
  3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?

Update

According to @nanofarad's suggestion, I've tried this circuit:

enter image description here

Although I don't yet have these FETs, so I used two 5LP01SP instead of them.

Please note, R1 is 1K to stay on the safe side.

Normally the powerbank provides a negative voltage on its output when turned off (-3V).

However with this circuit, there is only -0.8V on its output. I would say there is a 2V drop (not drop technically as the voltage is being increased, but I don't know how to express it)!

Why this drop is being introduced on negative voltage? Should not this circuit block reverese current, and therefore also voltage dropping?

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET. It had a flyback diode between drain and source (which is not illustrated here.)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output.)

Unluckily, BT1 is providing negative voltage when it is turned off (-3V.)

I came across with this circuit by TI:

enter image description here

I have some question about this, and I couldn't really find answers:

  1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
  2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
  3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?

Update

According to @nanofarad's suggestion, I've tried this circuit:

enter image description here

Although I don't yet have these FETs, so I used two 5LP01SP instead of them.

Please note, R1 is 1K to stay on the safe side.

Normally the powerbank provides a negative voltage on its output when turned off (-3V).

However with this circuit, there is only -0.8V on its output. I would say there is a 2V drop (not drop technically as the voltage is being increased, but I don't know how to express it)!

Why this drop is being introduced on negative voltage? Should not this circuit block reverese current, and therefore also voltage dropping?

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET. It had a flyback diode between drain and source (which is not illustrated here.)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output.)

Unluckily, BT1 is providing negative voltage when it is turned off (-3V.)

I came across with this circuit by TI:

enter image description here

I have some question about this, and I couldn't really find answers:

  1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
  2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
  3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?
added 729 characters in body
Source Link
Daniel
Daniel
  • 1k
  • 13
  • 24

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET. It had a flyback diode between drain and source (which is not illustrated here.)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output.)

Unluckily, BT1 is providing negative voltage when it is turned off (-3V.)

I came across with this circuit by TI:

enter image description here

I have some question about this, and I couldn't really find answers:

  1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
  2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
  3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?

Update

According to @nanofarad's suggestion, I've tried this circuit:

enter image description here

Although I don't yet have these FETs, so I used two 5LP01SP instead of them.

Please note, R1 is 1K to stay on the safe side.

Normally the powerbank provides a negative voltage on its output when turned off (-3V).

However with this circuit, there is only -0.8V on its output. I would say there is a 2V drop (not drop technically as the voltage is being increased, but I don't know how to express it)!

Why this drop is being introduced on negative voltage? Should not this circuit block reverese current, and therefore also voltage dropping?

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET. It had a flyback diode between drain and source (which is not illustrated here.)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output.)

Unluckily, BT1 is providing negative voltage when it is turned off (-3V.)

I came across with this circuit by TI:

enter image description here

I have some question about this, and I couldn't really find answers:

  1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
  2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
  3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET. It had a flyback diode between drain and source (which is not illustrated here.)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output.)

Unluckily, BT1 is providing negative voltage when it is turned off (-3V.)

I came across with this circuit by TI:

enter image description here

I have some question about this, and I couldn't really find answers:

  1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
  2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
  3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?

Update

According to @nanofarad's suggestion, I've tried this circuit:

enter image description here

Although I don't yet have these FETs, so I used two 5LP01SP instead of them.

Please note, R1 is 1K to stay on the safe side.

Normally the powerbank provides a negative voltage on its output when turned off (-3V).

However with this circuit, there is only -0.8V on its output. I would say there is a 2V drop (not drop technically as the voltage is being increased, but I don't know how to express it)!

Why this drop is being introduced on negative voltage? Should not this circuit block reverese current, and therefore also voltage dropping?

deleted 40 characters in body; edited title
Source Link
JRE
JRE
  • 73.6k
  • 10
  • 112
  • 195

Reverse current blocking - how do these dual FETs workingwork?

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET and is having. It had a flyback diode between drain >|and source (which is not illustrated here).)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output).)

HoweverUnluckily, unluckily BT1 is providing negative voltage when it is turned off (-3V).)

So I came across with this circuit (byby TI):

enter image description here

I have quite some question about this, and I couldntcouldn't really find answers:

1.) What kind of MOSFETs are being used? (N, or P channels?)

I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.

2.) Is this only a drawing difference? With other words, which one of these two would be my Q1? Left one or the right one? (I believe right one based on the flyback diode).

3.) I can understand how this blocks reverse current when gates are on GND. However when they are opened up, I understand the right FET: current is flowing from source to drain (from left-to-right on the figure). But what happens with the left FET? Why would current flow from drain to source in a P-FET?

  1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
  2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
  3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?

Reverse current blocking - how these dual FETs working?

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET and is having a flyback diode between drain >| source (which is not illustrated here).

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output).

However, unluckily BT1 is providing negative voltage when it is turned off (-3V).

So I came across with this circuit (by TI):

enter image description here

I have quite some question about this, and I couldnt really find answers:

1.) What kind of MOSFETs are being used? (N, or P channels?)

I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.

2.) Is this only a drawing difference? With other words, which one of these two would be my Q1? Left one or the right one? (I believe right one based on the flyback diode).

3.) I can understand how this blocks reverse current when gates are on GND. However when they are opened up, I understand the right FET: current is flowing from source to drain (from left-to-right on the figure). But what happens with the left FET? Why would current flow from drain to source in a P-FET?

Reverse current blocking - how do these dual FETs work?

I have a fairly simple application:

enter image description here

Q1 is a P-Channel MOSFET. It had a flyback diode between drain and source (which is not illustrated here.)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output.)

Unluckily, BT1 is providing negative voltage when it is turned off (-3V.)

I came across with this circuit by TI:

enter image description here

I have some question about this, and I couldn't really find answers:

  1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
  2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
  3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?
Source Link
Daniel
Daniel
  • 1k
  • 13
  • 24