Timeline for Why is the hold time given by the delay through the 3-input NAND gate in this D FF?
Current License: CC BY-SA 4.0
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| Oct 2 at 7:01 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| Mar 4, 2022 at 21:36 | comment | added | Dave Tweed | That's why I said "(if it isn't already)". If the other two inputs to gate 3 are high, then a rising edge on clock will create a falling edge on P2. If P2 is already low, then D is already disabled and hold time is not an issue at all. | |
| Mar 4, 2022 at 19:47 | comment | added | EE18 | @DaveTweed It's not clear to me why Clk = 1 drives P2 low necessarily. This seems to be D-dependent. | |
| Mar 4, 2022 at 18:42 | comment | added | Dave Tweed | Simple way to look at it: Rising edge of clock drives P2 low (if it isn't already), and this is what disables the path from D, driving P4 high. If D goes low-to-high before P2 goes low, it could create a low-going glitch on P4 that perturbs the state. | |
| Mar 4, 2022 at 18:00 | answer | added | across | timeline score: 1 | |
| Mar 4, 2022 at 17:32 | history | asked | EE18 | CC BY-SA 4.0 |