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Consider the (somewhat optimized) implementation of a (positive edge-triggered) D flip-flop given in the attached image (which comes from the book by Brown and Vranesic). It is stated that the setup time for the FF is the delay through gates 4 and then (plus) 1. This makes sense since, if D changes inside of that window, then P4 could potentially change without the change being reflected in P3.

What I am confused about is the statement that the hold time is given by the delay through gate 3. Supposing that I change D inside of that time (the way I have been reasoning about hold and setup times is to reason by the contrapositive, in a sense), I can't see why that would mess things up. Can someone help me out?

enter image description here

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  • \$\begingroup\$ Simple way to look at it: Rising edge of clock drives P2 low (if it isn't already), and this is what disables the path from D, driving P4 high. If D goes low-to-high before P2 goes low, it could create a low-going glitch on P4 that perturbs the state. \$\endgroup\$
    – Dave Tweed
    Commented Mar 4, 2022 at 18:42
  • \$\begingroup\$ @DaveTweed It's not clear to me why Clk = 1 drives P2 low necessarily. This seems to be D-dependent. \$\endgroup\$
    – EE18
    Commented Mar 4, 2022 at 19:47
  • \$\begingroup\$ That's why I said "(if it isn't already)". If the other two inputs to gate 3 are high, then a rising edge on clock will create a falling edge on P2. If P2 is already low, then D is already disabled and hold time is not an issue at all. \$\endgroup\$
    – Dave Tweed
    Commented Mar 4, 2022 at 21:36

1 Answer 1

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Say setup is met, and assume gate3 is slower than gate1.

Before positive edge of clock:
P1 = P2 = 1 stable
gate4 acts as inverter, so its output P4 = D' is also stable.
This means the input D' is waiting at P4(input to gate3 and gate1) for the clock to go positive level.

After the positive edge of clock:
The input D' just has to travel gate3 before latching in. So you must keep D stable for a minimum delay of gate3. Otherwise the changed D(gate4 input) will overwrite the old stable D'(gate3 processing) before it has a chance to go beyond gate3 - you lost the stable old bit that is being processed by gate3 because the new data arrived too early and disturbed the old data under process by gate3.

More likely the FF goes into metastable state because the input voltage to latch may not be a perfect 0 or 1 during latching when hold fails.

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