Timeline for Is a high resistor value between GPIO pads acceptable?
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 15, 2022 at 21:24 | comment | added | Aaron Kimball | @Mr.Snrub interesting idea but not what I was intending. My purpose is "if I want to reprogram this existing assembly in a way that uses SPI" instead of the 10-line port. So making an assembly-time decision to enable one or the other doesn't help; I'm trying to get more future-proof flexibility out of a post-assembly board if that makes sense. And user4574 to that extent, I don't have a target SPI frequency in mind; if adding resistors means "it works but only < 1 MHz" or some other limit, that is acceptable. | |
| Apr 15, 2022 at 16:32 | answer | added | jp314 | timeline score: 1 | |
| Apr 15, 2022 at 14:39 | comment | added | user4574 | What frequency do you intend to operate the SPI bus and parallel bus at? | |
| Apr 15, 2022 at 14:33 | answer | added | Sim Son | timeline score: 2 | |
| Apr 15, 2022 at 7:23 | comment | added | Mr. Snrub | How about making this a stuffing option? Most board designers I know would do it this way: give the layout four 0Ω resistors (or better yet one quad-pack of 0Ω resistors) leading to the MOSI/MISO/SCK/CS lines, and another set of 0Ω resistors going to the standard I/O pins. When the board is assembled, you install the 0Ω resistors which correspond to the pins you'll actually be using, and the other resistors are left unpopulated. Does that work for your needs? | |
| Apr 14, 2022 at 22:55 | comment | added | Aaron Kimball | PS - in case it matters, I plan to use a 4-layer stackup (signal/gnd -- gnd -- power -- signal/gnd) | |
| Apr 14, 2022 at 21:57 | history | asked | Aaron Kimball | CC BY-SA 4.0 |