Timeline for classic RISC pipeline: Why does memory access stage comes before register file write back?
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jun 13, 2022 at 17:54 | comment | added | jonk | @lousycoder I am "working" right now and cannot join an active discussion. In a few hours, yes. Just not now. | |
| Jun 13, 2022 at 17:51 | comment | added | lousycoder | Let us continue this discussion in chat. | |
| Jun 13, 2022 at 17:43 | vote | accept | lousycoder | ||
| Jun 13, 2022 at 17:42 | comment | added | jonk | @lousycoder The SW instruction provides a pointer register, an immediate offset to add to the pointer register (using the ALU) to create a data memory address, and a register containing the data to write to memory, and then performs that operation. So it doesn't just set things up. It performs the data write before the instruction retires. And yes, there are lots of register operations. But data memory reads and writes are handled with specialized instructions. That said, functional units (and instructions) can be added. So today's boundaries are not tomorrow's. | |
| Jun 13, 2022 at 12:46 | comment | added | lousycoder | I'm not good at using jargons correctly, by WB I mean that SW instruction performs the write operation to the external memory / or it at least provides the data to be written, right? In this way, we load the particular data using LW instruction, perform any desired math / logical ops or/and use branch/jumps and store the final answer using SW instruction, right? | |
| Jun 13, 2022 at 8:59 | comment | added | jonk | @lousycoder As far as what the SW instruction goes, all it does is use the ALU to compute an address while also passing along a register value. This gets to the Data Memory at the EX/MEM stage, where both the address and the register value are presented to the memory system at thee same time. There's no need for WB here. | |
| Jun 13, 2022 at 8:56 | comment | added | jonk | @lousycoder Don't worry about what you've "heard." RISC is not "a single thing." If you want to see a case where the folks went absolutely maximum towards RISC then look at the DEC Alpha processor. That baby is absolutely CRAZY-minded towards RISC. The absolute opposite is the MSP430 from TI. They also say the MSP430 is RISC. That's total crap. It isn't even close. So do NOT listen to folks telling you what RISC is and what RISC is not. Only Patterson and Hennessey have the ultimate say on the topic (my opinion.) (I've met both of them.) | |
| Jun 13, 2022 at 8:49 | comment | added | lousycoder | Usually what I have heard is that RISC based computers copy everything on registers, operate on them and write back the final result to the memory outside the processor. Thus, in effect, arithmetic ops like add, mul can't directly access the data memory and the result of these would be stored in reg file which ultimately gets written back to the separate memory using the "store" assembly op. Am I right? | |
| Jun 13, 2022 at 8:44 | comment | added | lousycoder | Okay, so can I say that reg file read must occur "before" data memory write (in case of Store instruction) and data memory read must occur "before" reg file write (in case of Load instruction), right? | |
| Jun 12, 2022 at 4:14 | history | answered | jonk | CC BY-SA 4.0 |