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Electrical Engineering
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lousycoder
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question
10
How were custom chips designed in the days prior to the arrival of FPGAs as hardware emulation devices? [closed]
Sep 12, 2021
question
9
How does the current processor technology with low clock rates (<10 GHz) deals with mmWave (>10 GHz) technology used in 5G?
Jul 7, 2021
question
4
Interaction between multiple blocking assignment and non-blocking assignment running in separate procedural blocks in Verilog
Mar 9
question
3
Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?
Feb 17
question
2
How do I get more clarity on the meaning of "integration" in VLSI?
Sep 19, 2022
question
1
SSD lifespan is often expressed in terms of TBW (Terabytes Written), does that include read cycles?
Aug 19, 2021
question
1
Do wire/net type constructs in Verilog map to programmable interconnects/ switching matrix of FPGA?
Jul 26, 2022
question
1
How do I interpret DisplayPort blanking interval timing diagrams?
Aug 23, 2022
question
1
How do I create custom signal in waveform config file for a big Boolean expression made of many signals/expressions in an "if else" block in Vivado?
Oct 3, 2023
question
1
Navigating race condition in Verilog using blocking assignment
Oct 15, 2023