Timeline for ADC chip for multiple simultaneous conversions
Current License: CC BY-SA 4.0
20 events
| when toggle format | what | by | license | comment | |
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| Jul 14, 2022 at 14:31 | comment | added | D.A.S. | It may be a steep learning curve rather than choose an integrated more expensive solution, | |
| Jul 12, 2022 at 3:42 | answer | added | PStechPaul | timeline score: 2 | |
| Jul 11, 2022 at 18:52 | comment | added | Kyle B | With respect, and acknowledging I don't know anything about you .... In my experience every time an ME tries to spearhead an EE project, it fails. You don't know what you don't know. It takes literally YEARS for a newly graduated EE to get a really good handle on how this stuff all works and how to master it... Taking a course doesn't make you an EE. I don't design injection molds for the same reason.... | |
| Jul 11, 2022 at 17:23 | comment | added | Tim Williams | Can you explain why "simultaneous" sampling is needed -- and more importantly, define what interval should count as "simultaneous"? | |
| Jul 11, 2022 at 16:30 | review | Suggested edits | |||
| Jul 11, 2022 at 20:33 | |||||
| Jul 11, 2022 at 15:09 | comment | added | TimWescott | You probably want to consult with an EE. "Same instant of time" is meaningless in engineering terms, because zero timing jitter can't be achieved any more than you can machine a bar of 2024 to exactly 1". Please edit your question with the acceptable relative jitter between the sample times. Also -- and this does have strong bearing on the issue -- include the precision you need, either in number of bits or in the overall range (i.e. -2.5 to +2.5V) and amount of acceptable error (i.e. 1mV). | |
| Jul 11, 2022 at 14:59 | answer | added | DKNguyen | timeline score: 9 | |
| Jul 11, 2022 at 14:58 | answer | added | TonyM | timeline score: 4 | |
| Jul 11, 2022 at 14:55 | review | Close votes | |||
| Jul 17, 2022 at 3:04 | |||||
| Jul 11, 2022 at 14:53 | comment | added | Spehro 'speff' Pefhany | You can get a single-chip simultaneous-sampling ADC (just search and peruse datasheets) with at least 8 inputs, and synchronize multiple chips. This can be important when you need precise phase relationships between signals. You need to define "instant in time"- there will be a bandwidth of the ADC with anti-aliasing filter. Even without the anti-aliasing filter there will be an analog bandwidth. | |
| Jul 11, 2022 at 14:49 | comment | added | brhans | Are you really sure that it's important that the channels are all samples at the same instant in time? Unless you're deliberately under-sampling, your anti-alias filters should ensure that your signals are not changing much during each sample period. If you have a single fast ADC capable of say 1MSPS then you can sample all 15 channels within 15us. So if your 'overall' sample rate for the entire batch of 15 channels is 1kHz then you've sampled all 15 channels within the 1st 15us of each 1ms period. | |
| Jul 11, 2022 at 14:41 | comment | added | user1850479 | There are a lot of possible solutions here that will all do what you want, but have you considered the simplest solution of getting a 6 channel ADC, wiring up your 6 inputs, and being done with it? Most complex options might get away with lower expense, but KS/s this is probably a pretty inexpensive device regardless. | |
| Jul 11, 2022 at 14:32 | history | edited | JRE | CC BY-SA 4.0 |
added 18 characters in body
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| Jul 11, 2022 at 14:32 | answer | added | Elliot Alderson | timeline score: 2 | |
| Jul 11, 2022 at 14:31 | comment | added | Jens | What is the desired resolution and sample rate? | |
| Jul 11, 2022 at 14:31 | history | edited | TonyM | CC BY-SA 4.0 |
Spelling and grammar. Clarifications.
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| Jul 11, 2022 at 14:31 | comment | added | Linkyyy | You can get ADCs with multiple inputs. | |
| Jul 11, 2022 at 14:24 | history | edited | Elliot Alderson | CC BY-SA 4.0 |
deleted shopping question
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| S Jul 11, 2022 at 14:22 | review | First questions | |||
| Jul 11, 2022 at 14:31 | |||||
| S Jul 11, 2022 at 14:22 | history | asked | ASG | CC BY-SA 4.0 |