Timeline for CAN Bus error frame in PWM driver
Current License: CC BY-SA 4.0
20 events
| when toggle format | what | by | license | comment | |
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| Aug 22, 2022 at 5:49 | answer | added | OzkulA | timeline score: 1 | |
| Aug 22, 2022 at 5:01 | comment | added | OzkulA | @RohatKılıç, Unfortunately, not much has changed since you worked :) I often use your library, Rohat Hocam. | |
| Aug 22, 2022 at 4:56 | comment | added | OzkulA | @Seir, As in the schematic I attached, there are 2x60.4 Ohm split termination resistors on both sides. | |
| Aug 22, 2022 at 4:53 | comment | added | OzkulA | @Lundin, First I suspected the internal oscillator the most. But in 2 layers, a few of the products with the same card were working without any problems, but we got CAN error frames in most of them. These frames increase in temperature and become unable to respond to the command anymore. But as you said, using an external oscillator seems like a much better option anyway. | |
| Aug 22, 2022 at 4:45 | comment | added | OzkulA | @Jens, Yes. I looked the signals but I saw the frames clearly. | |
| Aug 18, 2022 at 9:49 | comment | added | Rohat Kılıç | I see some schematic symbols that I created when I was working for that company :) | |
| Aug 18, 2022 at 7:50 | comment | added | Velvet | With CAN communication issues the first thing I check is the bus termination. When powered off, what is the resistance between CANH and CANL? It should be in the ballpark of 60Ω. | |
| Aug 18, 2022 at 7:48 | comment | added | SamGibson♦ | @OzkulA - Hi, You wrote an "answer" but it wasn't actually the answer to your original question. It was additional information, so it has been added to your question as an edit (i.e. an update) instead. Unless you are writing the full and final answer to your own question (i.e. unless you have solved the problem yourself and don't need further help) please don't use the box labeled "Your Answer" below. Instead please edit the question to add new information. (This is one way that Stack Exchange differs from forums. Please see the tour and help center for more rules.) Thanks. | |
| Aug 18, 2022 at 7:44 | history | edited | SamGibson♦ | CC BY-SA 4.0 |
appended answer 631565 as supplemental
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| Aug 18, 2022 at 6:42 | comment | added | Lundin | @OzkulA Running from the internal RC is questionable at 250kbps. What's the oscillator's accuracy? It shouldn't be worse than 1.3% or that's your problem right there. | |
| Aug 18, 2022 at 5:19 | comment | added | OzkulA | @Lundin, I added my CAN circuit + filtering. Bus speed is 250kbps, derived from internal RC osc. | |
| Aug 15, 2022 at 11:58 | comment | added | Lundin | Please also include a schematic of the transceiver + filtering and termination components. Depending on their value, those caps might be problematic. Also, what's the clock source for your CAN, internal RC or external quartz oscillator? | |
| Aug 12, 2022 at 23:16 | comment | added | Jens | Did you have a look at the CAN lines via oscilloscope? Can you see artefacts there if you trigger the scope by PWM rising or falling edge? | |
| Aug 12, 2022 at 10:52 | comment | added | OzkulA | I connect the layers at the other half side of the picture i shared. At the return path of Input filter Inductor pin. I am aimed that high current PWM pulses at the MOSFET's sources don't impact the MCU and other IC's grounding. I seperated the planes and connect them only return path pin of the input filter inductor. | |
| Aug 12, 2022 at 9:03 | comment | added | HansPeterLoft | Why do you have two ground planes? I cannot see really via stiching between your power and digital ground plane, so where do you connect them together? Normally you go with Signal-GND-PWR-Signal layers for a 4 layer PCB and you NEVER route any trace on the GND plane and only as few as possible on the PWR plane (never interrupt a traces return path, which means never go over a gap in the ground or power plane with a referencing signal trace). | |
| Aug 12, 2022 at 8:23 | history | edited | ocrdu | CC BY-SA 4.0 |
added 74 characters in body; edited title
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| Aug 12, 2022 at 8:14 | comment | added | OzkulA | I add my 4layer pcbs' inner layer layouts. Second one has a problem too. Do you think the planes are mis designed? | |
| Aug 12, 2022 at 8:11 | history | edited | OzkulA | CC BY-SA 4.0 |
added 464 characters in body
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| Aug 12, 2022 at 7:01 | comment | added | HansPeterLoft | Looks like you don't use a solid ground plane and route over ground gaps, so there are huge return current loops and that might lead to the problems. | |
| Aug 12, 2022 at 6:43 | history | asked | OzkulA | CC BY-SA 4.0 |