Timeline for How to manage MOSFET spikes in low side switch switch
Current License: CC BY-SA 4.0
17 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 9, 2023 at 2:36 | history | edited | superN8 | CC BY-SA 4.0 |
added 396 characters in body
|
| Mar 8, 2023 at 19:31 | vote | accept | superN8 | ||
| Mar 8, 2023 at 8:36 | history | edited | winny | CC BY-SA 4.0 |
English
|
| Mar 8, 2023 at 7:37 | comment | added | greybeard |
@SteKulov: and the gate capacitance of the MOSFETs assuming they aren't dwarfed by the 10 nF parallel to the sources? Oh, schematics' have changed.
|
|
| Mar 8, 2023 at 7:32 | comment | added | tobalt | There are some conventions for schematics. Usually you draw NMOSFETs with their drains up and source down, because that naturally fits another convention of having the voltage drop from positive to negative, as you go down in the schematic. | |
| Mar 8, 2023 at 7:28 | answer | added | tobalt | timeline score: 0 | |
| Mar 8, 2023 at 2:43 | answer | added | Simon Fitch | timeline score: 5 | |
| Mar 7, 2023 at 23:07 | history | edited | superN8 | CC BY-SA 4.0 |
deleted 348 characters in body
|
| Mar 5, 2023 at 4:04 | comment | added | Ste Kulov | More info here on IBIS: electronics.stackexchange.com/a/573907 . Also, Getting rid of those caps is a good idea. A voltage source right into a capacitor doesn’t do anything except produce massive current spikes whenever there’s a high dv/dt (i.e. when your GPIO switches) | |
| Mar 5, 2023 at 4:03 | comment | added | Ste Kulov | Keep in mind that your model of your GPIO (independent voltage source w/ 10ns rise/fall time) is not a good model for a typical CMOS output. If you’re going to go into this detail of seeing how much current is being spiked at each transition, then you need to create a more accurate model of your actual GPIO. I personally don’t think your spikes are likely to be a problem, but if you want to do a more thorough analysis and make a better model you can look at the manufacturer’s website for IBIS models or you can do some bench testing/measurements to get some rise times and a Thevenin equivalent. | |
| Mar 5, 2023 at 4:01 | comment | added | Ste Kulov | The spikes are a function of the rise/fall time of your GPIO switching and the gate capacitance of the MOSFETs. You form an RC circuit with any equivalent resistance in series with the gate, so a larger series resistor would slow the charging of the gate and reduce the spikes. The gate charging is also going to depend on the load in the drain, which is why you get a similar effect when changing the load. The gate capacitance is weird and non-linear. It's also going to change quite a bit between MOSFETs, so only use the model of the actual part you intend to use. | |
| Mar 5, 2023 at 3:13 | comment | added | superN8 | I replaced the inductors with resistors and that seemed to behave the same as increasing the values of the resistors in the LED Strip / gate resistors. I also removed the decoupling caps as those seemed to make the spikes larger. The load is not affected by the spikes as much as the voltage sources, but still sees spikes of about 700uA. I'm worried about spikes on the GPIO mostly, and also protecting the RGB controllers | |
| Mar 5, 2023 at 0:08 | comment | added | Ste Kulov | Replace the inductors with resistors and start with 100ohm then keep playing with the values. I see all your current measurements are for the independent voltage sources. Are you worried about spikes there, or are you also getting spikes through your loads (the resistors + diodes)? | |
| Mar 4, 2023 at 5:48 | history | became hot network question | |||
| Mar 4, 2023 at 1:01 | history | edited | superN8 | CC BY-SA 4.0 |
added 555 characters in body
|
| Mar 3, 2023 at 21:39 | answer | added | Voltage Spike♦ | timeline score: 4 | |
| Mar 3, 2023 at 21:35 | history | asked | superN8 | CC BY-SA 4.0 |