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I have written Verilog code for a JK flip flop (gate level modelling), and I am getting an error in the output (error means x propagation). Why are my q and qb outputs x (the unknown Verilog value)? For example, when k=` and j=0, I expect q=0.

module jk (q,qb,j,k,clk);
    output q,qb;
    input j,k,clk;
    wire [1:0]a;
    nand (a[0],j,clk,qb), (a[1],k,clk,q);
    nand (q,a[0],qb), (qb,a[1],qb);
endmodule

module tb;
wire q,qb;
reg j,k,clk;
jk ff (.j(j), .k(k), .clk(clk), .q(q), .qb(qb));

initial begin
    clk=0;
    forever #5 clk=~clk;
end

initial begin
        j=1'b0; k=1'b1;
    #10 j=1'b1; k=1'b0;
    #10 j=1'b1; k=1'b1;
    #10 j=1'b0; k=1'b0;
    #10 $finish;
end
endmodule

I have written Verilog code for a JK flip flop (gate level modelling), and I am getting an error in the output (error means x propagation). Why are my q and qb outputs x (the unknown Verilog value)? For example, when k=1 and j=0, I expect q=0.

module jk (q,qb,j,k,clk);
    output q,qb;
    input j,k,clk;
    wire [1:0]a;
    nand (a[0],j,clk,qb), (a[1],k,clk,q);
    nand (q,a[0],qb), (qb,a[1],qb);
endmodule

module tb;
wire q,qb;
reg j,k,clk;
jk ff (.j(j), .k(k), .clk(clk), .q(q), .qb(qb));

initial begin
    clk=0;
    forever #5 clk=~clk;
end

initial begin
        j=1'b0; k=1'b1;
    #10 j=1'b1; k=1'b0;
    #10 j=1'b1; k=1'b1;
    #10 j=1'b0; k=1'b0;
    #10 $finish;
end
endmodule

I have written Verilog code for a JK flip flop (gate level modelling), and I am getting an error in the output (error means x propagation).

module jk (q,qb,j,k,clk);
    output q,qb;
    input j,k,clk;
    wire [1:0]a;
    nand (a[0],j,clk,qb), (a[1],k,clk,q);
    nand (q,a[0],qb), (qb,a[1],qb);
endmodule

module tb;
wire q,qb;
reg j,k,clk;
jk ff (.j(j), .k(k), .clk(clk), .q(q), .qb(qb));

initial begin
    clk=0;
    forever #5 clk=~clk;
end

initial begin
        j=1'b0; k=1'b1;
    #10 j=1'b1; k=1'b0;
    #10 j=1'b1; k=1'b1;
    #10 j=1'b0; k=1'b0;
    #10 $finish;
end
endmodule

I have written Verilog code for a JK flip flop (gate level modelling), and I am getting an error in the output (error means x propagation). Why are my q and qb outputs x (the unknown Verilog value)? For example, when k=` and j=0, I expect q=0.

module jk (q,qb,j,k,clk);
    output q,qb;
    input j,k,clk;
    wire [1:0]a;
    nand (a[0],j,clk,qb), (a[1],k,clk,q);
    nand (q,a[0],qb), (qb,a[1],qb);
endmodule

module tb;
wire q,qb;
reg j,k,clk;
jk ff (.j(j), .k(k), .clk(clk), .q(q), .qb(qb));

initial begin
    clk=0;
    forever #5 clk=~clk;
end

initial begin
        j=1'b0; k=1'b1;
    #10 j=1'b1; k=1'b0;
    #10 j=1'b1; k=1'b1;
    #10 j=1'b0; k=1'b0;
    #10 $finish;
end
endmodule

I have written Verilog code for a JK flip flop (gate level modelling), and I am getting an error in the output (error means x propagation).

module jk(q,qb,j,k,clk);
output q,qb;
input j,k,clk;
wire [1:0]a;
nand(a[0],j,clk,qb),(a[1],k,clk,q);
nand(q,a[0],qb),(qb,a[1],qb);
endmodule

module tb;
wire q,qb;
reg j,k,clk;
jk ff(.j(j),.k(k),.clk(clk),.q(q),.qb(qb));
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
j=1'b0;k=1'b1;
#10 j=1'b1;k=1'b0;
#10 j=1'b1;k=1'b1;
#10 j=1'b0;k=1'b0;
#10 $finish;
end
endmodule

I have written Verilog code for a JK flip flop (gate level modelling), and I am getting an error in the output (error means x propagation).

module jk (q,qb,j,k,clk);
    output q,qb;
    input j,k,clk;
    wire [1:0]a;
    nand (a[0],j,clk,qb), (a[1],k,clk,q);
    nand (q,a[0],qb), (qb,a[1],qb);
endmodule

module tb;
wire q,qb;
reg j,k,clk;
jk ff (.j(j), .k(k), .clk(clk), .q(q), .qb(qb)); 

initial begin
    clk=0;
    forever #5 clk=~clk;
end 

initial begin
        j=1'b0; k=1'b1;
    #10 j=1'b1; k=1'b0;
    #10 j=1'b1; k=1'b1;
    #10 j=1'b0; k=1'b0;
    #10 $finish;
end
endmodule