Timeline for Why do I get the a.out 1:syntax error when I run Icarus Verilog simulation?
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
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| Jul 9, 2023 at 10:53 | history | edited | toolic | CC BY-SA 4.0 |
added 18 characters in body; edited tags
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| Jul 9, 2023 at 10:50 | comment | added | toolic |
@jsotola: This is expected. The iverilog command generates a file named a.out when the -o option is not used.
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| Jul 9, 2023 at 10:47 | answer | added | toolic | timeline score: 2 | |
| Jul 8, 2023 at 17:14 | comment | added | jsotola |
where are you getting the filename a.out? ... your source files have names starting with round_robbin ... the module also has that same name
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| Jul 8, 2023 at 17:01 | history | edited | jsotola | CC BY-SA 4.0 |
edited title
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| Jul 8, 2023 at 15:40 | history | edited | Dave Tweed | CC BY-SA 4.0 |
fix formatting
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| S Jul 8, 2023 at 15:33 | review | First questions | |||
| Jul 8, 2023 at 16:57 | |||||
| S Jul 8, 2023 at 15:33 | history | asked | TejaSantosh Koliparthi | CC BY-SA 4.0 |