Timeline for Why do I get the a.out 1:syntax error when I run Icarus Verilog simulation?
Current License: CC BY-SA 4.0
3 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jul 9, 2023 at 14:08 | history | edited | toolic | CC BY-SA 4.0 |
added 140 characters in body
|
| Jul 9, 2023 at 11:00 | history | edited | toolic | CC BY-SA 4.0 |
added 117 characters in body
|
| Jul 9, 2023 at 10:47 | history | answered | toolic | CC BY-SA 4.0 |