Timeline for 2d arrays specification in verilog
Current License: CC BY-SA 3.0
10 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 13, 2014 at 9:12 | review | Suggested edits | |||
| Apr 13, 2014 at 10:55 | |||||
| May 6, 2013 at 21:48 | vote | accept | Bledi Boss | ||
| May 1, 2013 at 18:00 | answer | added | Greg | timeline score: 2 | |
| Apr 28, 2013 at 21:22 | comment | added | Joe Hass | Why don't you try loading array[0] with 7'h55 and array[1] with 7'h2A, then see what you get for array[0][0] and array[0][1]? | |
| Apr 28, 2013 at 17:52 | comment | added | Bledi Boss | NO I don't get any errors | |
| Apr 28, 2013 at 17:51 | comment | added | Joe Hass | What happens when you simulate your code? Did you get any errors when you tried to compile your proposed line of code at the bottom of your question? | |
| Apr 28, 2013 at 17:36 | comment | added | Bledi Boss | MostSignificantBit | |
| Apr 28, 2013 at 17:33 | comment | added | Dave Tweed | Which bit do you consider to be the "first", the MSB or the LSB of a word? You need to define your bit and word indices accordingly. | |
| Apr 28, 2013 at 17:22 | review | First posts | |||
| Apr 28, 2013 at 17:42 | |||||
| Apr 28, 2013 at 17:02 | history | asked | Bledi Boss | CC BY-SA 3.0 |