# 2d arrays specification in verilog

I am trying to define a 2d array in verilog but I don't understand them very well in the way they are assigned. What I mean is if I define an array like

reg [6:0] array[7:0]


I hope I defined an array with 8 rows and 7 columns. If a number is assigned lets say:

array[0] = 7'b1100000; array[1] = 7'b0101000;


In what order are they placed? My intention is to read the first bit in every row. So if I read like this do I get the result:

array[0][0]-->should give 1(the first bit of first row)
array[0][1]-->should give 0(the first bit of second row)


So is my assignment way correct? Or should I play with the order like:

reg array[0:6] array[0:7]

• Which bit do you consider to be the "first", the MSB or the LSB of a word? You need to define your bit and word indices accordingly. – Dave Tweed Apr 28 '13 at 17:33
• MostSignificantBit – Bledi Boss Apr 28 '13 at 17:36
• What happens when you simulate your code? Did you get any errors when you tried to compile your proposed line of code at the bottom of your question? – Joe Hass Apr 28 '13 at 17:51
• NO I don't get any errors – Bledi Boss Apr 28 '13 at 17:52
• Why don't you try loading array[0] with 7'h55 and array[1] with 7'h2A, then see what you get for array[0][0] and array[0][1]? – Joe Hass Apr 28 '13 at 21:22

Get yourself a copy of the latest SystemVerilog (supperset of Verilog) LRM. Available for from IEEE.

Read section 7.4 "Packed and unpacked arrays". Pay special attention to section 7.4.4 and 7.4.5.

Below is example code:

parameter P = 6:0;
parameter U = 7:0;
// {[packed_range]} name {[unpacked_range]};
reg       [P]      array        [U]; // U unpacked of packed sized P
reg   [1:0] [P]   array2; // 1:0 packed of packed size P
reg   [0:1] [P]   array3; // 0:1 packed of packed size P
initial begin
array[0] = 7'b1100000; // assign the packed portion of unpacked
array[1] = 7'b0101000;
array2[0] = array[0]; array2[1] = array[1];
array3[0] = array[0]; array3[1] = array[1];
//                  U  P
$display("%b",array[0][0]); // prints 0 -- U's entry 0, P's entry 0$display("%b",array[0][1]); // prints 0 -- U's entry 0, P's entry 1
$display("%b",array[0][3]); // prints 0 -- U's entry 0, P's entry 3$display("%b",array[1][3]); // prints 1 -- U's entry 1, P's entry 3
$display("%d",array[0][6:4]); // prints 6 -- U's entry 0, P's range 6:4$display("%d",array[1][6:4]); // prints 2 -- U's entry 1, P's range 6:4
$display("%d",array[1]); // prints 28 -- U's entry 1, P's range 6:0 (implied) //$display("%d",array[1:0][0]); // ** ILLEGAL
//$display("%d",array); // ** ILLEGAL cannot print unpacked$display("%b",array2[1][3]); // prints 1 -- [1:0]'s entry 1, P's entry 3
$display("%d",array3[1]); // prints 28 -- [0:1]'s entry 1, P's range 6:0 (implied)$display("%b",array2); // prints 01010001100000 -- implies {array2[1],array2[0]}
\$display("%b",array3); // prints 11000000101000 -- implies {array3[0],array3[1]}
end