Timeline for Parsing variable-sized data in 32-bit datastream
Current License: CC BY-SA 4.0
17 events
| when toggle format | what | by | license | comment | |
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| Sep 23, 2023 at 14:37 | vote | accept | John Smith | ||
| Sep 6, 2023 at 0:45 | vote | accept | John Smith | ||
| Sep 23, 2023 at 14:37 | |||||
| Sep 1, 2023 at 21:07 | answer | added | Kuba hasn't forgotten Monica | timeline score: 2 | |
| Sep 1, 2023 at 16:29 | history | edited | jsotola | CC BY-SA 4.0 |
removed the "does anyone know?" type of question
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| Sep 1, 2023 at 15:13 | history | edited | JYelton | CC BY-SA 4.0 |
edited title
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| Sep 1, 2023 at 13:48 | comment | added | Simon Richter |
I have the same problem in my sha256 block, and I've generated the combinatorics with a procedure and a loop -- basically, I have four blocks that each accept the old aligner state, a single byte and a byte enable signal, and output an aligned word and a new aligner state. Because there are no register stages between the steps, the optimizer flattens that.
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| Sep 1, 2023 at 13:45 | comment | added | John Smith | The stream resets if 9 times 0xffffffff is recieved. | |
| Sep 1, 2023 at 13:45 | answer | added | Jaredo Mills | timeline score: 2 | |
| Sep 1, 2023 at 13:42 | comment | added | jonathanjo | How can you synchronise? If you start the receiver in the middle of stream (or there was any noise) is there any way to discover which is the type byte? | |
| Sep 1, 2023 at 13:40 | history | edited | toolic |
edited tags
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| Sep 1, 2023 at 13:40 | comment | added | John Smith | The data stream runs at 125Mhz | |
| Sep 1, 2023 at 13:39 | comment | added | asdfex | Please add some numbers. "Native" can be anything between 1 kHz and 1 GHz | |
| Sep 1, 2023 at 13:38 | comment | added | John Smith | Native speed, as in every clock cycle the data is valid. So if I would change the width to 8 I would need a 4x clock which unfortunately is not realistic :( | |
| Sep 1, 2023 at 13:36 | comment | added | asdfex | What is the datarate of the stream? Is it too fast to process it in 8 Bit width inside the FPGA? | |
| Sep 1, 2023 at 13:33 | comment | added | John Smith | @jonathanjo As indicated in the question both the type and length are a single byte. I cannot change the stream width or apply back pressure. | |
| Sep 1, 2023 at 13:29 | comment | added | jonathanjo | Have you considered converting to a byte stream (or even bit stream)? You don't describe the synchronisation -- how will you know when we're at the beginning of a frame? Are you able to choose the protocol? How many types are there? | |
| Sep 1, 2023 at 13:15 | history | asked | John Smith | CC BY-SA 4.0 |