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Timeline for Peripheral interface design

Current License: CC BY-SA 4.0

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Feb 6 at 15:18 history edited TonyM CC BY-SA 4.0
Clarifications.
Feb 1 at 0:15 comment added TonyM @David00, glad you think so and thanks for showing that with an upvote :-)
Jan 31 at 20:20 comment added David00 This is a an elegant solution. I've realised that by focusing on 8 bit regs, I didn't think about pre-loading 4 bits into a H type reg. The fog has cleared. Thank you for your patience and guidance throughout, much appreciated.
Jan 31 at 14:18 history edited TonyM CC BY-SA 4.0
Added diagram.
Jan 31 at 1:18 comment added David00 Thanks, will need to look at properly in the morning.
Jan 31 at 1:06 comment added TonyM @David00, revised, this should do what you want.
Jan 31 at 1:02 history edited TonyM CC BY-SA 4.0
added 876 characters in body
Jan 31 at 0:03 comment added David00 Yes. I know that every byte sent from the CPU must comprise some control bits and some data bits. The end goal is to encode data in the sent byte so as to end up with four 8-bit data bytes into [A] thru [D]. I’d considering sending nibbles, and reassembling them at Y using a fourth hi/lo control line/bit in the sent byte. But I think I need an extra control bit as a clock/enable for Y. I’m wondering if 1 bit in the sent byte could define/change the split between data and control bits to get around this.
Jan 30 at 23:44 comment added TonyM @David00, I must have misunderstood your question, then. So you could pass data up the 8 wires in nybbles. And you want to load data into 4x 8-bit latch. Are both those right?
Jan 30 at 23:37 comment added David00 Thanks for the suggestion. Doesn’t this load 4 bits of data into one of the 4 data end-points [A] thru [D]? But each of them is 8-bits wide. I’m struggling with the nibbles to byte assembly at Y, as I don’t have enough derived control lines.
Jan 30 at 22:53 history answered TonyM CC BY-SA 4.0