Timeline for Dissect code related to "Convergent rounding: Round half to even" written in SystemVerilog
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 9 at 4:45 | comment | added | quantum231 | Are you able to figure out how this actually performs the rounding operation? I thought that we need to look at the bit just after decimal point (or the one just after OWID) but this code does not do that. | |
| Apr 7 at 17:39 | vote | accept | quantum231 | ||
| Apr 7 at 10:24 | comment | added | toolic | @quantum231: The original question was focused. Instead of adding new questions into the question, I recommend accepting this answer, then posting a new question. For the new question, I recommend running simulations, then asking a specific qustion if there is something about the simulation you do not understand. | |
| Apr 6 at 12:30 | comment | added | quantum231 | (1) Why is there no IF statement to accomodate the case where the input is exactly half-way e.g 1.5, 2.5 e.t.c. (2) Why do we need the third part {(IWID-OWID-1){!i_data[(IWID-OWID)]}}, aren't these bits always supposed to be 0? (3) Since SystemVerilog can easily add two logic vectors together when they have different size, why do we need the {(OWID){1'b0}}? | |
| Apr 4 at 23:51 | comment | added | quantum231 | Thanks, I have update the questions with three things that are specifically confusing for me. | |
| Apr 4 at 22:29 | history | answered | toolic | CC BY-SA 4.0 |