Timeline for Weird SRAM failures when heat is applied to the system and when probed
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 19 at 18:20 | vote | accept | Oscyzilla | ||
| Aug 19 at 18:20 | answer | added | Oscyzilla | timeline score: 2 | |
| May 22 at 16:16 | comment | added | Justme | @Oscyzilla Have you measured if the STM32 memory write and read cycle timing are within specificatiom for the memory data sheet? Have you measured if the memory can achieve the bus cycle timings in the datasheet? You may also have faulty or counterfeit memory depending on from where you bought it. | |
| May 22 at 14:52 | comment | added | Oscyzilla | @Jens Decoupling caps are rated at X5R, placed as closed as possible to both memory and uC, have appropriated voltage rating. Placed the recommended value of capacitors as per datasheets. | |
| May 22 at 14:52 | comment | added | Oscyzilla | @Kartman I will open up a channel w/ST on this. My signal integrity simulations only accounted for looking at crosstalk and time domain analysis. In depth signal integrity analysis was not done due to lack of schedule/budget :( | |
| May 22 at 14:48 | comment | added | Oscyzilla | @Justme I will be requesting this parameter be updated. As I am aware, we are running at HCLK of 180 MHz. I would like to see what would happen if we increase timing parameters in bit error tests. | |
| May 22 at 14:15 | comment | added | Jens | Are the decoupling capacitors X7R type and are there enough? The impact on capacitance variation during temperature change is large compared to the impact on the IC. | |
| May 22 at 9:15 | comment | added | Kartman | You’ve done simulations etc, but do the actual pcbs perform as per your simulations? You might be able to submit your design files to ST to validate. | |
| May 22 at 4:25 | comment | added | Justme | So what are the timing parameters used for the external memory bus? Does it work if you add +1 to any of the current parameters? | |
| May 22 at 3:45 | comment | added | Ale..chenski | Meeting timing specifications (with account for amplitudes and shifts in receiver thresholds) over full temperature range (and over spectrum of devices from approved vendor list) per plan of record and approved specifications is pretty much the day-to-day job of professional designers and production and validation engineers. Ensuring healthy margins is a key. Apparently your interface design has little to no margins. | |
| May 22 at 3:15 | history | asked | Oscyzilla | CC BY-SA 4.0 |