Weird SRAM failures when heat is applied to the system and when probed

Question

I'm providing assistance on a project that is encountering some interesting behavior on an SRAM memory device when environmental temperature goes up or when someone probes/touches lines associated with the data lines (if touching, ESD safety is being followed). Our setup is a custom board that utilizes the STM32F429BIT uC along with the IS61WV102416DBLL-10BLI SRAM and MT28EW128ABA NOR Flash. We have the SRAM and NOR Flash ADDR and DATA lines tied to the same FMC bank. For routing, we made sure that flyback routing was followed, length matching was met, and single ended controlled impedance of 50 Ohms was followed for all DATA/ADDR/CTRL lines. Signal integrity was done on Hyperlynx. Signal integrity pointed out a couple of crosstalk violations from some ADDR lines, so the layout was updated to fix these problems and were re-simulated to assure it was addressed.

I would like to point out that on a previous revision, no length matching, controlled impedance, and signal integrity was taken into account in regards to the routing of the SRAM/NOR Flash. Random failures would occur involving the SRAM and NOR Flash at power up/programming/in the field. It was discovering this that I recommended the team to proceed with the re-spin of the board to address potential layout mishaps that could be causing numerous issues.

Upon receiving our new boards back, SW tested the boards by running a read, write, clear test on the SRAM. At room temperature, the SRAM was running fine and did not report any errors throughout the test. We increased the surrounding temperature by carefully using a heat gun at low heat from a distance. We noticed that once the board temperature reach 85 F, the SRAM would start to show failures.

I'm a little perplexed that a small increase in temperature would lead to issues like this. I plan on making sure we are meeting timing requirements with our write and erase process, however, it's perplexing that some heat could potentially cause bit errors.

Does anyone have any experience where their memory devices on their custom board performed simple bit error tests at room temperature and then failed at slightly higher temperatures? Curious to get your insights as to what might have happened and what was done to resolve the issue.

I can provide detail schematics/drawings when I go back into the office tomorrow.

Answer 1

Answering my own question in case anyone out there might come across the same problem:

There was no issue with the timing specification from a SW or HW perspective nor was there an issue with the PCB layout of the design. The root cause as to why the SRAM was behaving erratically when touched or when there was an increase in temperature was due to the fact that the LB# and UB# signals on the SRAM were misconfigured from the software end. The software team confirmed the signals controlling LB# and UB# from the microcontroller were not used and was therefore left as analog inputs to conserve power (from a HW perspective, I am unsure what their thought process was in not controlling LB# and UB#). It makes sense as to why the SRAM devices was behaving erratically when touch and heat was applied. With the appropriate updates from the software side in controlling the LB# and UB#, the SRAM device is working as intended, even at higher temps and when touched.