I am confused by the voltage reading in this simulation as VCE reads as 907V which means almost the entire voltage is dropped over the VCE at the transistor. I assumed that the VCE should be a fixed voltage and the rest should be dropped over the resistor. When I play with different values, then sometimes this is the case and sometimes not. But it seem unpredictable.
How is voltage split between load resistor and C -> E on transistor?
I assumed that the VCE should be a fixed voltage and the rest should be dropped over the resistor. When I play with different values, then sometimes this is the case and sometimes not. But it seem unpredictable.
It depends on the operating mode of the transistor.
If the transistor is in saturation mode, then you can assume (very roughly) that the \$V_{ce}\$ is something like 0.2 V, and the rest of the drop is across the load.
If the transistor is in forward active mode, then the current into the collector is effectively fixed (at \$\beta I_b\$, that is, a fixed multiple of the base current). Then the drop across the load is whatever it drops due to that current (\$(1\ k\Omega)(97\ mA)\$ in your example), and the remaining drop is across the transistor.
Typically you work out which mode the transistor is in (once you know the b-e junction is forward biased) by first guessing it's in forward active. If the calculation for forward active gives a c-e drop less than ~0.2 V, then you know the mode is not actually forward active, and the transistor is in saturation instead.
