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In an I2C network, I am using an AVR microcontroller (AtMega328p) as a Master and I hooked it up to multiple sensors as Slaves, such as the TMP102, SI1145, MPU9250, among others. All of these sensors have pins to signal interrupts to the microcontroller.

Assuming these interrupts never come at once, would the following HW configuration make any sense? :

  • (assuming all the sensors produced on the falling edge of the signals)
  • tie the interrupt pins directly to the SCL line
  • set up an Interrupt Serice Routine reacting to the falling edge of the SCL, enable it
  • wait for a negative edge on the SCL. At this point, a sensor has tripped a treshold
  • disable the ISR, normal I2C polling of the sensor ensues

The goal would be to save up space on the PCB design and use existing tracks.

Granted, one would need to poll all the sensors to know who interrupted by pulling SCL low.

My example used SCL, but is the difference between SCL and SDA important in this case? The I2C communication could be reset / timeout when the uC restarts communication with the sensors.

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    \$\begingroup\$ How do you ensure interrupts do not occur during a data transfer? It all boils down to this. If you can ensure that by some protocol, the chances you don't need interrupts at all hit the ceiling. \$\endgroup\$
    – Janka
    Commented Jun 5, 2017 at 22:56
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    \$\begingroup\$ So if all your interrupt lines are tied to SCL and an interrupt occurs, how do you clear the interrupt if you cannot access the device? Interrupt SCL low. You have to be able to write to it to clear it. Tie all your INT to a separate INT line. \$\endgroup\$
    – StainlessSteelRat
    Commented Jun 5, 2017 at 23:07
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    \$\begingroup\$ Intel Architecture Labs used a separate open-drain interrupt in their SMBus Smart Battery extention to I2C. They do indeed use interrupt polling through the device responding to the reserved SMBAlert address, and the open-drain SDA bus ensures the interrupting devices are priority encoded. This only works if the device is SMBus compliant however. \$\endgroup\$
    – MarkU
    Commented Jun 5, 2017 at 23:32
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    \$\begingroup\$ SDA falling edge while SCL high is always a Start Condition - you can't use SDA to assert interrupt status because you will lock the I2C bus. \$\endgroup\$
    – MarkU
    Commented Jun 5, 2017 at 23:35
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    \$\begingroup\$ Excellent comments. My initial starting point was that interrupts were cleared by HW after x ms, which is not the case. Moreover, one needs to look out for unintentionally producing a start condition. Please post an answer so I can approve it. Thank you for your precious support! \$\endgroup\$
    – Mihai Galos
    Commented Jun 6, 2017 at 7:49

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