In an I2C network, I am using an AVR microcontroller (AtMega328p) as a Master and I hooked it up to multiple sensors as Slaves, such as the TMP102, SI1145, MPU9250, among others. All of these sensors have pins to signal interrupts to the microcontroller.
Assuming these interrupts never come at once, would the following HW configuration make any sense? :
- (assuming all the sensors produced on the falling edge of the signals)
- tie the interrupt pins directly to the SCL line
- set up an Interrupt Serice Routine reacting to the falling edge of the SCL, enable it
- wait for a negative edge on the SCL. At this point, a sensor has tripped a treshold
- disable the ISR, normal I2C polling of the sensor ensues
The goal would be to save up space on the PCB design and use existing tracks.
Granted, one would need to poll all the sensors to know who interrupted by pulling SCL low.
My example used SCL, but is the difference between SCL and SDA important in this case? The I2C communication could be reset / timeout when the uC restarts communication with the sensors.