I'd like to know if this MOSFET switches design is okay

Question

I have a design where the power of my circuit comes from a 12V battery and I use the energy from the battery to turn on/off a solenoid valve using an ESP32 (which outputs 3.3V from it's GPIO).

In general the circuit will have some other elements that require power from the battery.

The logic of my circuit is as follows: If the battery voltage drops below a certain threshold, disconnect the power of the battery from every other component in the circuit BUT the ESP32 (which has a buck converter that converts 12V -> 3.3V)

Now, to do this, I'm considering using a MOSFET for switching on/off the current flow from the 12V from the battery to the rest of the circuit when this condition is met, I'm adding a flyback schottky diode for safety (because I'll have some inductive loads).

Now, I'm not entirely sure if I should connect the drain of my first MOSFET to the source of the second MOSFET. The second MOSFET will be used to turn on/off the solenoid valve using another GPIO of the ESP32.

I'm sorry if I'm not making myself clear, I'm struggling with my english over here. I'm attaching a schematic that I've been simulating on multisim.

The circuit on the left is the switch that cuts off the power from the circuit of the right. The circuit on the right is the one that turns on/off the solenoid valve (modeled as an array of inductances and resistors that I found on research gate)

Answer 1

If you connect the drain of Q2 to the source of Q1, then Q1 will be disabled when the gate of Q2 is pulled low. (assuming they are N-MOSFET's). If this is your intent, then S2A must be at logic zero to disable the relay. (It's not very clear what else you wish to disconnect.)

Also I advise you to increase the resistors between the gates and ground to between 100K to 470K because 10K will reduce voltage a bit and as it's already only 3V, it's better not to reduce it. Better not to see less than 3V at the gate when you want the MOSFET to conduct optimally. 100K to 470K will ensure that the gate is at logic zero if the output is high impedeance (not pulled low neither high) without acting too much like a voltage divider as 10K would.

If you can, try to apply more than 3V to the gates. You can use 12V to the gates. But it may complicate the circuit... or simplify it. I don't know.

Answer 2

A couple of comments/suggestions.

First, have you considered using a solid-state relay (SSR) to turn ON|OFF the +12 VDC power? From your description it seems an SSR is a good option.

Second, I recommend you use a comparator with hysteresis for your "low battery" detector circuit (Reference1, Reference2, Reference3). Note that a battery's voltage changes for loaded (high current) and unloaded (low or zero current) conditions. Imagine that you choose a voltage of 11.8 VDC as your "low battery" threshold voltage. The battery, when it is connected to its full load, slowly discharges until its terminal voltage dips below 11.8 VDC. Your comparator circuit detects the condition \$V_{battery} \le V_{threshold}\$ and your circuit disconnects +12 VDC power from the load, which causes a sudden reduction in output current at the battery, which causes a sudden increase in voltage at the battery's terminals—e.g., perhaps the voltage rises to 11.9 VDC. The comparator (if it DOES NOT have hysteresis) now notices the battery voltage is 11.9 VDC, which is greater than the threshold voltage, and your circuit reconnects the load the +12 VDC supply. Once again, the battery is loaded down, its voltage dips below \$V_{threshold}\$, your circuit disconnects +12 VDC power from the load, and so on. At this point the circuit is oscillating, rapidly turning OFF|ON the +12 VDC power to the downstream load, which is bad for the downstream load and for transistors Q1 and Q2.