DAC used as multiplier

Question

I have tested a circuit with DAC (MCP4922). Using it as multiplier, reference sine wave is applied to VREF pin and sine wave of same frequency is applied as digital input to DAC, I didn't went deeper at that point but output was pretty close what I could get from a analog multiplier.

Since I want now to take it further, I have doubt whether what i did is right with regard to settling time as I am continuously varying the VREF input, which in most cases is constant. (No data is available is data sheet in this context)

Please share some views whether it is a reliable technique, because analog multiplier chips cost almost same/greater than DAC, but DAC offers some flexibility for testing and experimenting.

Answer 1

The parameter you are interested in is specified in table 5V AC/DC CHARACTERISTICS of the MCP4921/4922 datasheet. There are two bandwidth rows, indicating values of 450 KHz and 400 KHz.

TL;DR

Of course, the data is available in data sheet, in the context of your question.

To understand what exactly the row

**Input Amplifier (VREF Input)**
...
Multiplier Mode | f_VREF | — | 450 | — | kHz | V_REF = 2.5V ±0.2Vp-p, Unbuffered,
-3 dB Bandwidth |        |   |     |   |     | G = 1

does mean, first pay attention to the top row of this table:

**Electrical Specifications:** Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, 
output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF TA = -40 to +85°C. 
Typical values at +25°C.

In the Multiplier Mode row the VDD is not specified, so VDD = 5V; V_REF is specified, so V_REF = 2.5V replaces the default 2.048V; output buffer gain is specified, so G = 1 replaces the default G = 2; etc.

In the configuration that is specified in this bandwidth row, the input signal with DC = 2.5V and AC = 0.2V·sin(2π·f·t) (composed of pure sine waveform of amplitude 0.2V plus 2.5V constant voltage) is fed to the V_REF input of the Input Amplifier. The row specifies that the typical frequency f, at which the AC component AC = 0.2·sin(2π·f·t) is attenuated by 3 dB, is 450 kHz.

In a similar way, you can read the next row with G = 2. It specifies that the typical -3 dB bandwidth value with multiplier mode is 400 kHz when Gain Select bit is set to zero (GA = 0, G = 2).

Now, the multiplication with multiplier DAC is performed on two factors. One (multiplicand) is an analog voltage fed to the VREF input, the other (multiplier) is a number fed via Serial Data Input. While the bandwidth is clearly defined for the analog input (VREF), it has not that obvious definition for the numerical input. The datasheet timing parameter for effects of this inherently non-linear input is settling time (4.5 us) and it cannot be directly translated to something similar to bandwidth.

It is a documentary aspect of your question.

The signaling aspect can be explained with the design principle of the DAC. Note that this device architecture is a resistive string DAC. So, after the switches are settled, the resistive string network is simply a passive linear circuit (voltage divider), and the input signal (VREF) only attenuates when passing this circuit. Its frequency spectrum does not deteriorate in any significant degree (especially when in unbuffered mode), and it is fed to the Output Op Amps (see Block Diagram) in all its entirety.

The datasheet does not specify the frequency parameters when working with buffered inputs, just mentions, in section 4.1.2 VOLTAGE REFERENCE AMPLIFIERS, that

Buffered mode provides a very high input impedance, with only minor limitations on the input range and frequency response.

and these limitations are most probably Too small to quantify as the datasheet notes elsewhere.