3
\$\begingroup\$

I've transformed this circuit:

schematic

simulate this circuit – Schematic created using CircuitLab

In this one:

enter image description here

I am aware that the input is V_in and the output is the current which enters in drain. I am aware also that here I have considered the V_out as the output of my analysis.

Now let assume that I've found the literal equations of the V_out/V_in, neglecting Cgd and Cds.

  1. Does it make any sense doing such analysis in frequency for stability purposes?
  2. Or should be done on the output current over the input voltage?
  3. While I can estimate the output resistance of the circuit (saw from drain), the one related to the opamp really matters for stability analysis?

Just to address better who want to help, I want to know only how usually is made such analysis. For brevity, I'm not asking for the analysis itself.


My goal is to achieve these informations by calculus and verify them on the field later. I've already made a SPICE simulation and Matlab plot for the transfer function of V_out/V_in. That can be put and commented, if needed.

\$\endgroup\$
2
  • \$\begingroup\$ thexeno, you mention "analysis in frequency for stability" - what does this mean? Are you interested in stability margins? In this case, you must analyze the LOOP GAIN in the frequency domain. If you just want to know "stable yes/no" a time domain analysis (Tran analysis, step response) is sufficient. \$\endgroup\$
    – LvW
    Jul 5, 2015 at 8:10
  • \$\begingroup\$ Now I have some time for this project. @LvW I want to find the stability margins. Yes, I need the loop gain. --> But the question is how to find it. I tried few month ago, and I posed the results here: electronics.stackexchange.com/questions/146297/… Can you say something about its correctness? \$\endgroup\$
    – thexeno
    Aug 1, 2015 at 16:05

1 Answer 1

1
\$\begingroup\$

The mosfet gate resistance is not negligible, so I suggest you include it in your model. Otherwise it looks OK.

\$\endgroup\$
8
  • \$\begingroup\$ So, the resistance of the opamp output can be neglected? \$\endgroup\$
    – thexeno
    Jan 20, 2015 at 23:12
  • \$\begingroup\$ Wouldn't the mosfet gate resistance be multiple megohms? I think it is negligible for many purposes in this type of circuit. \$\endgroup\$
    – user57037
    Jan 21, 2015 at 19:34
  • \$\begingroup\$ Op-amp resistance is usually assumed to be zero because of the feedback loop to the inverting input. This causes the op-amp to push or pull as hard as possible to equalize it's two inputs. Including a driving resistance would only make sense if the MOSFET were being driven by a constant voltage source, which the op-amp is not. @mkeith, We are only interested in the switching behavior of the op-amp - not the steady-state resistance of the MOSFET gate, which is close to infinite: best modeled as a capacitor as the above model shows. \$\endgroup\$
    – Otto Hunt
    Jan 21, 2015 at 23:58
  • \$\begingroup\$ @mkeith, We are only interested in the switching behavior of the op-amp - not the steady-state resistance of the MOSFET gate, which is close to infinite: best modeled as a capacitor as the above model shows. \$\endgroup\$
    – Otto Hunt
    Jan 23, 2015 at 1:47
  • \$\begingroup\$ @user901750, I agree that it is best modeled as a capacitor. But please note that you first say "the mosfet gate resistance is not negligible." Then you say "the steady state resistance of the MOSFET gate... is close to infinite." If you agree that it is close to infinite and can be ignored, then why did you first say that it is not negligible? \$\endgroup\$
    – user57037
    Jan 23, 2015 at 6:49

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.