Does this current buffer analysis make sense?

I've transformed this circuit:

simulate this circuit – Schematic created using CircuitLab

In this one:

I am aware that the input is V_in and the output is the current which enters in drain. I am aware also that here I have considered the V_out as the output of my analysis.

Now let assume that I've found the literal equations of the V_out/V_in, neglecting Cgd and Cds.

1. Does it make any sense doing such analysis in frequency for stability purposes?
2. Or should be done on the output current over the input voltage?
3. While I can estimate the output resistance of the circuit (saw from drain), the one related to the opamp really matters for stability analysis?

Just to address better who want to help, I want to know only how usually is made such analysis. For brevity, I'm not asking for the analysis itself.

My goal is to achieve these informations by calculus and verify them on the field later. I've already made a SPICE simulation and Matlab plot for the transfer function of V_out/V_in. That can be put and commented, if needed.

• thexeno, you mention "analysis in frequency for stability" - what does this mean? Are you interested in stability margins? In this case, you must analyze the LOOP GAIN in the frequency domain. If you just want to know "stable yes/no" a time domain analysis (Tran analysis, step response) is sufficient.
– LvW
Jul 5, 2015 at 8:10
• Now I have some time for this project. @LvW I want to find the stability margins. Yes, I need the loop gain. --> But the question is how to find it. I tried few month ago, and I posed the results here: electronics.stackexchange.com/questions/146297/… Can you say something about its correctness? Aug 1, 2015 at 16:05