In the following circuit, the three ideal operational amplifiers are polarized such that their saturation voltages are ± 20 VDC. The other components of the circuit are resistors, one of them being adjustable (the Rx).

enter image description here

What is the limit condition for adjusting Rx so that the output voltage does not saturate?

A) 3kΩ < Rx < 4 kΩ. B) Rx > 5 kΩ. C) Rx < 5 kΩ. D) 4 kΩ < Rx < 5 kΩ. E) Rx < 4 kΩ.

My attempt:

Consider \$V_{down}\$ and \$V_{up}\$ the voltage on Buffers inputs are \$\frac{40}{3}V\$ and \$\frac{20}{R_x + 1}V\$ respectively.

So the Summing Amplifier is:

$$V_{out} = -2k\left(\frac{\frac{20}{R_x+1}}{1k}+\frac{\frac{40}{3}}{2k}\right)$$

Consider that \$V_{out} \leq -20V\$ (I'm not for sure this statement)

$$-20 \geq -2k\left(\frac{\frac{20}{R_x+1}}{1k}+\frac{\frac{40}{3}}{2k}\right)\Rightarrow 10 \leq \frac{20}{Rx+1}+\frac{20}{3}\Rightarrow \frac{1}{Rx+1}+\frac{1}{3} \geq \frac{1}{2}\\ \frac{6}{Rx+1}+2 \geq 3\Rightarrow 6\geq R_x+1\Rightarrow R_x \leq 5k\Omega$$

I find the letter C) but the correct answer is letter B).

What did I miss?


1 Answer 1


Your bottom buffer drives the output to -13.33V. The top buffer can drive it only 6.66V lower before hitting -20V. The top buffer has a gain of two through the last stage, so it must be kept BELOW 3.33V.

The voltage divider with the potentiometer then has to keep the center tap node BELOW 3.33V. That means the pot value has to be at LEAST 5 times the 1K value of the fixed resistor, or that node will be pulled too high.

There's no danger of saturating the output on the plus side, since it inverts and there's no way to give it a negative input in this circuit.

  • \$\begingroup\$ you mean the bottom buffer drives 13.33V (positive)? \$\endgroup\$
    – miguel747
    Commented Sep 20, 2019 at 19:46
  • 1
    \$\begingroup\$ Yes, but the final stage inverts it. \$\endgroup\$ Commented Sep 23, 2019 at 14:01
  • \$\begingroup\$ Ty. Last question: I can't see that the upper buffer delivery gain 2 instead 1. I can only visualize the bottom has 13.33v in its output and upper one has 6.66v (max). \$\endgroup\$
    – miguel747
    Commented Sep 23, 2019 at 14:06
  • \$\begingroup\$ The buffer itself has a gain of one, but it drives the output stage with a gain of -2. The two paths have different gains because one has a 1K input resistor on the final, whereas the other one has a 2K input resistor. \$\endgroup\$ Commented Sep 23, 2019 at 14:09

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