What happens at hardware level when we feed a code? [duplicate]

Question

I wanted to know what hardware is installed in 8051 such that whenever i write a program it accepts it and execute it. My query is what happens at the hardware level whenever i feed a program to 8051.

Answer 1

Opcode - the unique identifier for each possible instruction that a computer can run. Physically, it is a unique string of binary bits which is represented in Assembler as a token (so a human can read it without memorizing a string of ones and zeroes)

Program - a bunch of ones and zeroes (or low and high electrical signals) consisting of the sequence of opcodes and their arguments (numbers) to be executed when the system runs.

Program Memory - This physically stores the program. The ones and zeroes are physically stored in a configuration transistors. In SRAM, the transistors act as a form of latch to tie the node to either the positive voltage rail or GND, which represent either HI or LO.

In DRAM, the voltage is stored inside the parasitic capacitor that is parts of a transistor.

In flash, it is stored as a charge inside the structure of the transistor that modifies the transistor's behaviour. This might sound like a capacitor, but it isn't.

On a magnetic harddrive it is stored as the polarity of a ferromagnetic domain.

Opcode circuitry - the physical manifestation of the opcode. It is circuitry that reads the appropriate arguments that it will operate with or on from the instruction register, processes them, and loads the result somewhere. Each opcode has one and the this circuitry will processes the data and delivers the result into a register somewhere.

Instruction Register - the register that stores the instruction line which is about to be parsed and read/decoded/translated. It is loaded from wherever the program counter register is pointing at in the bits that form the program memory

Instruction Decoder - this circuitry reads the opcode ID field in the instruction register and sends a signal to activate the appropriate opcode circuitry which results in execution of the opcode.

It's basically a giant comparison engine that compares the current opcode against a bunch of available opcodes and if it matches, it outputs a signal to trigger the associated opcode circuitry. One way to imagine it is as an array of multi-bit comparators with each comparator having an output to trigger one of the opcode circuits. Each comparator examines the bits in the field of the instruction register that represents the opcode ID and compares it against a fixed value which is the bits for the opcode ID it is responsible for. If it matches, it fires a signal to the opcode circuitry to trigger it.

Or you can imagine it as a giant lookup table that takes the bits in the opcode ID field of the instruction register as an input. It's output consist of one signal line going to each opcode circuit to trigger it. The lookup table is such that only one signal line is active for any given valid input (after all, you don't want a single opcode to end up triggering two opcode circuits to run. That just doesn't make sense.)

The decoder also reads the bits in the fields of the instruction register that represent the arguments for that opcode and passes them on to the opcode circuitry so it knows what it is working with. It is a crazy, chip spanning network of signals. Alternatively, the opcode circuitry might directly access those other fields in the instruction register to obtain their operands.

So in a sense, it is just a highly evolved version of a circuit consiting of AND gate circuit where one input is fed with a toggle switch and the other input is fed with a 1 or 0, depending on when you want the activity to trigger, and the output feeds a circuit that "does something specific".