TL;DR - How do I determine the appropriate inductor size to filter out signals at 115.2 kHz? Is the channel frequency determined by the baud rate or the signal rise time?

Edit -10/5/2020

Looks like people want a little more background on design/reqs/idea.

Overall architecture: Master Controller -- Coax Cable -- Sensor Controller.

  1. Half Duplex comms
  2. 8bits @ 1khz. Aiming for 115.2kpbs for overhead and future flexibility
  3. Deliver max 2.5W.
  4. Min 6V @ sensor end

Signal Chain

Master TX port - Inverter - Source Termination - AC couple cap - coax cable - AC couple cap - rectifier - Inverting Schmitt Trigger - Sensor RX Port

The goal is to reduce physical footprint at sensor side. AKA minimize filter inductor size and single supply operation.

Power Chain

Master 12V supply - Signal Blocking Filter - coax cable - Signal Blocking Filter - Sensor buck converter

From my understanding the signal blocking filter needs to minimize the energy sent by the signal chain into the power converters. AKA block most of the high frequency energy.

I've got some more inductors and supplies on the way to do some more experimentation, but insight into the theory would be useful.

End Edit 10/5/2020

I'm working on a project that utilizes a power over coax topology and after running some experiments with various inductor sizes I'm confused how to appropriately size it.

I calculated that in order to have 1kOhm impedance at 115.2kHz I need a 1.38mH inductor. L = impedance / angular_freq

I then tested the circuit by measuring input at C2 and output at C1 through 10 meters of RG178 coax cable. By swapping out various values of L2 (1.5mH, 0.75 mH, 0.5mH, 4.7uH, and 0H) I watched the response at C1.

I didn't see any change between 1.5mH thru 0.5 mH which tells me the inductor is greatly over sized. I clearly see no signal at 0H (wire) and a slight ripple at 4.7uH which tells me the inductor is too small.

From the oversized scenario I questioned whether my understanding of the channel frequency was incorrect.

Instead should I look at the rise time of the signal? At ~40nsec (25MHz) that results in an inductor value of ~8uH. But that seems too low given my results at 4.7uH.

Thanks for any insight.

enter image description here

0.5mH enter image description here

0.75mH enter image description here

4.7uH enter image description here

Source - https://passive-components.eu/wp-content/uploads/2017/10/Plenary-2-Subrt_Full_Paper_Power-over-Coax-Filter-Design-Challenges-for-Automotive-Vision-Applications_final.pdf

  • \$\begingroup\$ You can't just put a diode in series with a capacitor such as C1 and D2. After a few cycles the capacitor will charge up until the diode is always reverse biased. You need to put a resistor across D4 to represent the load. You will then need to bias the junction of C1 and D2. Depending upon you goals this may be a resistor to ground or to a boas voltage. A better circuit would be to couple C1 directly to a comparator (eg LM339) with the other input of the comparator to a suitable bias voltage. \$\endgroup\$ Oct 4, 2020 at 17:35
  • \$\begingroup\$ Hi Kevin, thanks for your feedback. How does the cap charge on the diode cathode side? Trying to understand the mechanism a bit more. And you're right about the comparator, I do have an inverting schmitt trigger hanging off D4 to bring back the square wave signal. The reason why I added the two diodes was because I don't want to deal with a dual supply and the signal seems to always dip below 0V on alternative pulses. Maybe there's a more elegant solution? \$\endgroup\$
    – ovd
    Oct 4, 2020 at 18:30
  • \$\begingroup\$ You don't show a scope trace after the diode. \$\endgroup\$ Oct 4, 2020 at 19:10
  • \$\begingroup\$ There is an elegant solution, it you need to define your problem in an elegant way from all the top down requirements instead of a bottoms up ... how do I select an inductor. This means source and load impedances and spectrum for power and data. Then protocol, Dc balanced( scrambled) or AC coupled protocol like Manchester, synchronous or asynchronous, burst or continuous , then desired power transfer and bit rate, and Bit error rate limit, error detection method and error correction method. been there done this , in 1977. With TV, 2 way data and 2 way baseband audio over 100m coax. \$\endgroup\$ Oct 4, 2020 at 20:09
  • \$\begingroup\$ I’m waiting for design specs on above, then a filter is simple to design for bandpass and bandstop. Consider using biphase. \$\endgroup\$ Oct 5, 2020 at 6:36

2 Answers 2


Reading between the lines, it sounds like you are trying to send a serial data stream (RS-232-ish). That requires a DC connection to the signal source, so this is just not going to work. Putting that aside, I will still answer your question.

The 115200 signal contains frequency content at 115200 and higher harmonics. If you want to pass DC, but block 115200, you want to place your filter cutoff frequency much lower than 115200. Much lower means by a multiple of 10x or more. This will insure the filter attenuation is substantial at 115200. In this case, since there isn't really a lower limit, I would suggest going 100x lower for your cutoff frequency. That will give you an cutoff of 1152 Hz as your target.

The rolloff from an LC filter is 40dB per decade (power). So by going 100 lower (two decades) you should be getting close to 80 dB of power attenuation. Hopefully that will be enough. If not, you can move the cutoff lower.

As far as the DC problem goes, one option might be to use a simple RF encoding scheme to send your signal over the wire as an AC signal. A simple on-off keying or two frequency FSK signal. Then you can still use RS232. You will just need to find a modulator/demodulator IC and put one on either end.

  • \$\begingroup\$ You're right about the serial data stream. UART TTL, but the idea isn't to hard connect to the downstream mcu but rather post-process with a schmitt trigger and then decode. As for the cut-off frequency - I'm trying to select the smallest inductors which leads me to find the highest cut-off frequency aka the data rate. However, I'm noticing that my assumptions here are incorrect as large variations in inductor values have little affect. \$\endgroup\$
    – ovd
    Oct 5, 2020 at 17:46
  • \$\begingroup\$ The cutoff frequency of the filter is determined by the inductor and capacitor. Did you calculate the cutoff frequency? \$\endgroup\$
    – user57037
    Oct 5, 2020 at 18:00
  • \$\begingroup\$ @ovd, to mkeith's point about DC, you have to look carefully at your long runs of 0s and 1s, compared to rapid toggles, and how the baseline level wanders if you are blocking DC in an on-off keying scheme. And I just realize one of the answers raises this point too. \$\endgroup\$
    – P2000
    Oct 5, 2020 at 20:51
  • \$\begingroup\$ To be absolutely explicit, RS232 cannot get through a DC blocking cap. It needs DC coupling to work. But you can just gate an AC waveform with your RS232 signal, then put a carrier detect circuit on the far side. Simple but effective. They sell IC's for this for use with optical RS232 links. \$\endgroup\$
    – user57037
    Oct 9, 2020 at 3:33

Since there will be contamination between power and signal, you need to define the acceptable cross_contamination.

Simple NRZ (on/off) signaling will allow low_pass_filtering, as long as you provide adequate settling time.

Each time constant of settling of NRZ will improve the flatness of the "1" or "0" by 9 dB (look up Neper).

If your signaling rate is 115,000 Hz, your bit period (in NRZ) is 9 microSeconds. There will be NEEDED ENERGY in that, down to DC, because you have not limited the # of consequtive "1"s or consequture "0"s.

So look at DC_balanced signaling methods, such as used to write onto harddrives.

  • \$\begingroup\$ As suggested it is better to ensure DC balance. I can be done in software. I suggest reviewing the techniques in airspayce.com/mikem/arduino/VirtualWire. \$\endgroup\$ Oct 4, 2020 at 17:38
  • \$\begingroup\$ OP is probably using RS232 type comm link. This has start bits to consider also. I don't think trying to balance 1's and zeros in software is going to solve it. OP should modulate the signal using on-off keying or FSK. \$\endgroup\$
    – user57037
    Oct 4, 2020 at 19:32
  • \$\begingroup\$ "Simple NRZ (on/off) signaling will allow low_pass_filtering" It's the HP filtering (DC blocking) in the signal path that will be the problem. \$\endgroup\$
    – P2000
    Oct 5, 2020 at 21:00

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