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for a very low power design I am looking for a normally-on switch (circuit) that conducts power (<2.0V, <20 mA) from 0V input voltage until switched off from a supervisor, once 2.0V are reached. The control signal will also be in the range of ~2.0 V. During my research for possible solutions I came across this article about designing zero-power normally-on switches.

The proposal is to use some (relatively expensive) "zero threshold MOSFETs" to realize this (see Fig.2): Fig.2, schematic

My understanding is that a high signal on VIN turns on Q1, which pulls the gate of Q2 to GND. However, this would not turn off Q2, since it has a threshold voltage of 0V or am I wrong?

Could someone clarify this for me or does anyone have another suggestion for implementing such a low-power switch?

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  • \$\begingroup\$ Any reason you're using expensive trimmed-Vt devices instead of just a regular depletion mode FET? \$\endgroup\$
    – Hearth
    Commented Jun 21, 2023 at 14:15
  • \$\begingroup\$ I thought I needed something like a depletion mode PMOS, which doesn't seem to exist but maybe I am making a thought error. I don't need the precisely trimmed features of the ALD FETs. I just want to use a positive-voltage control signal and have low leakage :) \$\endgroup\$
    – MoTex_42
    Commented Jun 21, 2023 at 14:21
  • \$\begingroup\$ Superficially I'd think some sort of cheap-n-cheerful N-channel JFET would work here. Something in the $0.50 each in small quantities range. But that would depend on whether you would require the switch to remain off when commanded off even if the (2V) supply falls below the JFET's Vgs cutoff. \$\endgroup\$
    – brhans
    Commented Jun 21, 2023 at 16:47
  • \$\begingroup\$ "this would not turn off Q2" It'll turn Q2 off enough to bring the voltage at the source terminal down to Vg, which means there's no voltage going to the load... If Q2 were "on", then Vds -> 0, Vs -> 1.5V and Vgs -> -1.5V which is a contradiction. So it must be off. \$\endgroup\$
    – Ben Voigt
    Commented Jun 21, 2023 at 19:32
  • \$\begingroup\$ Thank you @BenVoigt, that makes sense, thank you! \$\endgroup\$
    – MoTex_42
    Commented Jun 22, 2023 at 8:46

1 Answer 1

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The Q2 is connected as voltage follower (does not invert logic). Since the Vth of Q2 is 0V the source is always on same potential as gate.

Q1 is connected as inverter so whole circuit inverts the logic:
0V Vin = Load ON
+V Vin = Load OFF

Edit:

Regarding unabillity to fully close the Q2 you can try connection below. Warning, I never tried it, so research is up to you.
Q2 is depletion type. Q1 normal mosfet.
However circuit provides positive logic Vin ON = Load ON
Q1 carries the whole load current.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Thank you Michal! I played around with some depletion-mode MOSFETs but the problem is that I couldn't come up with a circuit that reduces the voltage on the load again. A single depletion NMOS with a grounded gate only limits the voltage to Vth... Any idea how to avoid the Vth=0 MOSFET? Thank you! \$\endgroup\$
    – MoTex_42
    Commented Jun 22, 2023 at 11:04
  • \$\begingroup\$ @MoTex_42 See edits. \$\endgroup\$
    – Michal Podmanický
    Commented Jun 22, 2023 at 11:33
  • \$\begingroup\$ Hi Michal, thank you very much for the effort! I just realized that I can actually live with the voltage across the load in this case. Therefore I decided to use a BSS159N depletion-mode MOSFET in front of the load (D= Input voltage, G=GND, S=Load). \$\endgroup\$
    – MoTex_42
    Commented Jun 22, 2023 at 13:44

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