I'm re-implementing a 1980's Microbee computer on an FPGA (see here: http://www.toptensoftware.com/fpgabee) and trying to figure out how to do the cassette port. Here's the schematics for the original Microbee cassette interface:

MicrobeeSchematic http://www.toptensoftware.com/fpgabee/MicrobeeCassettePortSchematic.png

I also found this description of it in a technical manual:

The cassette data output consists merely of an RC network which accepts a signal from DB1, pin 28 of the PIO. The signal is attenuated and then decoupled prior to sending it to the cassette recorder MIC input. This signal appears on pin 3 of the 5 pin DIN socket.

The cassette data input circuit is slightly more complicated. The input from pin 5 of the DIN socket passes first to an attentuator -decoupler. Following this is a CA3140 op-amp, to allow a wide range of input levels to be squared up before the signal is passed to pin 27 of the PIO, DBO. The two diodes across the inverting and non-inverting inputs to the op-amp clip any input signals greater than the diodes' forward voltage in either direction. The 47pF capacitor is required by the CMOS op-amp for precompensation.

My questions:

1. What does "de-coupled" in the description mean?
2. Would the same circuit work if connected to two of the I/O pins on a Xilinx Spartan 6 FPGA (through the PMod connector on a Nexys3) and if not, could it be adapted to make it work?