I have the following question regarding gate driving loss in a synchronous Buck. When we want to turn on HS or LS we have to charge their input capacitance \$C_{iss}\$. This is done through a driver which is supplied by \$V_{dd}\$ and in it simplest form it can be considered a CMOS inverter. So suppose we are turning on a LS nMOS gate driving loss \$P_{driving}\$ is defined as

\$P_{driving}=C_{iss}V_{dd}V_{batt}f_{sw}\$

A certain charge \$Q_{g}=C_{iss}V_{dd}\$ is provided by the driver and i'm totally fine with it.

Now we are using the pMOS of our CMOS inverter to provide a path between \$V_{dd}\$ and gate switch. pMOS is operating in triode mode so there will be some heat dissipation or power loss since it behaves like a resistor. At this point i would write average power

\$P_{driver}=V_{dd}I_{dd}\$

where \$I_{dd}\$ is the current flowing from supply to driver to gate switch. Now if i want to calculate total power loss regarding driving is it right to sum up the two power losses? I've read several application notes but this thing isn't clear : some mention an IC power loss (which should be \$P_{driver}\$), others never talk about actual power dissipated by driver. We need power to turn on the LS but we need power also for the driver. And gate driver power consumption impacts overral efficiency. Thanks for any help!