First, the drawing's a bit confusing. I infer that the J and K inputs are tied together ('J' label isn't lined up.)
That out of the way, you need to identify the critical path. That is, find the path that has the longest cumulative delay from clock to a flop input.
Yes, you are correct that all the flops change state together. But that's not the whole story.
Hint: notice the first two AND gates. They're connected head-to-tail so their delays add together to the input of the third Q2 flop. Let's call them AND1 and AND2. By inspection, together with Q0 clock-to-Q they are the critical path.
So we have:
- Tcq Q0 (leftmost flop) = 10ns
- Tpd AND1 = 10ns
- Tpd AND2 = 10ns
- Tsu J/K 2 (rightmost flop) = 0ns
These add up to 10 + 10 + 10 + 0 = 30ns. This gives us a max frequency of 1/30ns = 33MHz.
(And Dave Tweed came to the same conclusion when he saw this some years ago. 30ns it is.)