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FIFO (First In, First Out) is one way of managing a buffer for data

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Analyzing the SX1276 FIFO implementation

Section 4.1.2.3. gives a really good diagram of how the FIFO is addressed: When interacting with the FIFO via the SPI protocol, the SX1276 uses the FifoAddrPtr register to choose which byte to return … You can write to this register (its address is 0x0D) to set the address in the FIFO you wish to read and write to when addressing to the FIFO register (address 0x00). …
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