Search Results
| Search type | Search syntax |
|---|---|
| Tags | [tag] |
| Exact | "words here" |
| Author |
user:1234 user:me (yours) |
| Score |
score:3 (3+) score:0 (none) |
| Answers |
answers:3 (3+) answers:0 (none) isaccepted:yes hasaccepted:no inquestion:1234 |
| Views | views:250 |
| Code | code:"if (foo != bar)" |
| Sections |
title:apples body:"apples oranges" |
| URL | url:"*.example.com" |
| Saves | in:saves |
| Status |
closed:yes duplicate:no migrated:no wiki:no |
| Types |
is:question is:answer |
| Exclude |
-[tag] -apples |
| For more details on advanced search visit our help page | |
Results tagged with delay
Search options not deleted
user 9156
In electronics, a delay is an amount of time between two events. For example, the time between input and output of a signal in a circuit could be referred to as the processing time, or the delay. Sometimes delay is added deliberately, as in certain audio effects.
2
votes
1
answer
296
views
How can I simulate contamination delay in VHDL?
Propagation delay is simple to implement:
Out <= '1' after 3ns;
I tried to add contamination delay as such:
Out <= '1' after 3ns;
Out <= 'X' after 1ns;
so that Out would become undefined and then … [I'm using MultiSim to simulate, but this Quartus II link suggests it's normal to only observe the final assignment]
Is there a good way to simulate contamination delay? …
