Okay the proposed string worked as needed however still can't seem how I can work out the 1:14 & 3:16 I guess I could use buried bias from 3:15 and 2:14 or could use a single buried from 3:14

Correct me if wrong but would be then looking at the likes of say 2 blind bias for 1:2 & 15:16 and then the other layers would simply be connected via buried bias or an I looking at this complexly wrong?

@TomCarpenter, I see now, hmm. Is there a problem with having it all core layers? As you mentioned 1:2 & 15:16 & must be cores; however if I am to get 1:3 , 14:16 I wouldn't be able to make these if I used prepreg, so these have to also be cores. Regarding the crossing problem is there a way I could get around this? Or could I use buried via's perhaps?

@SunnyskyguyEE75 I understand the *+() & [a:...:b] stuff pretty fine. I tried your suggestion and it results in an unexpected ? referring to the * between 2 & 3

@TomCarpenter, I should think that stackup can be manufactured: See Aerospace article: aerospacepal.com/6-layer-pcb-stackup-emi-design Also the fabhouse I'm currently using is PCBWay. You can view their fabrication capabilities here: pcbway.com/capabilities.html

After reading through I noticed that when I did the schematic symbol I had grouped the DQSL, DQSU & CK positive and negative channels into 1 pin which wasn't good. I understand by the bits that 8 bits must stay with DQU0-7 & 8 bits must stay with DQL0-7. I'm still a little foggy in terms as to why on the left side chip you have DDR0_D0-D7 and then DDR0_D16-D23 instead of it being D8-D15 & vice versa on the other chip. So if able to explain that would be appreciated.