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I'm trying to manually fanout 5 bga's on my 6 layer board. Tried using Eagle's default Auto BGA router and kept coming up with problems regarding my additional layers being used but not enabled, I managed to fix this problem for my bottom ground layer but wasn't able to fix this for my power, middle signal & top ground layers however, so I just ended up doing this manually.

My 1st problem I'm encountering is the via pairing within the DRC layers tab. I've got it set to 6 layers and want to be use the following pairings:

  • 1-2
  • 1-3
  • 14-16
  • 15-16
  • 1-14
  • 3-16

I can add everything perfectly fine except the 2 last pairings (1-14 & 3-16). I can add one or the other; however if I add the other then I get an error either for invalid blind via or unexpected ':'

For example if I add the 3-16 pairing I will get the following setup string: ([3:[2:[1*2*3*14*15*16:3]:15]:14]) However if I then add 1-14 I get the following below error: enter image description here

If anyone knows how to get around this error and allow me to use all of the above pairings in one go, would be most appreciated.

My board stackup is as follow:

  • Top (1)
  • TGround (2)
  • Middle (3)
  • Power (14)
  • BGround (15)
  • Bottom (16)

Where Top, Middle and Bottom are signal layers whilst all signal lines relating to power will be located on the Power layer.

My 2nd problem I'm faced with is that out of the 5 bga's I'm working on 2 of them are completely different pitches for their ball arrays.

With one being 0.5mm & the other being 0.42mm (The other 3 bga's being 0.65mm) Which settings within DRC do I need to change so I can fanout the smallest bga?

An sub-question to this I'd like to ask how I would be able to manually place micro-via's? The auto bga router apparently does it but after scouring the web/autodesk eagle forums I've found no posts on how to manually place them.

Thank you for help @Tom Carpenter. I did manage to get a hold of a product specialise from AutoDesk who provided me with the following setup string: [14:[3:[2:(1+2+3+14+15+16):15]:14]:3]

My question to ask regarding this string as its purely 5 cores. Would it be possible at all to incorporate prepreg into 1:2, 3:14 & 15:16 or would this create an impossible to build design?

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  • \$\begingroup\$ maybe? [2 : (1 + (2 ∗ 3) + (14 ∗ 15) + 16) : 15] : p ∗ q means that layer p and q are combined with a core, while p + q means that these two layers are combined with prepreg. () signifies buried and through vias, while [a : ... : b] signifies blind vias \$\endgroup\$
    – D.A.S.
    Commented Jan 21, 2019 at 21:41
  • \$\begingroup\$ Question - have you checked with a board house that they can even make such a stackup? I don't think your desired stackup can be manufactured. \$\endgroup\$
    – Tom Carpenter
    Commented Jan 21, 2019 at 22:07
  • \$\begingroup\$ @TomCarpenter, I should think that stackup can be manufactured: See Aerospace article: aerospacepal.com/6-layer-pcb-stackup-emi-design Also the fabhouse I'm currently using is PCBWay. You can view their fabrication capabilities here: pcbway.com/capabilities.html \$\endgroup\$
    – Dragonfly3r
    Commented Jan 21, 2019 at 22:18
  • \$\begingroup\$ @SunnyskyguyEE75 I understand the *+() & [a:...:b] stuff pretty fine. I tried your suggestion and it results in an unexpected ? referring to the * between 2 & 3 \$\endgroup\$
    – Dragonfly3r
    Commented Jan 21, 2019 at 22:18
  • \$\begingroup\$ @Dragonfly3r I wasn't questioning your layer use, but rather that PCB houses to build vias that cross over like that.// Buried and blind vias have to be built by drilling the cores in stages. For example your 1:2 and 15:16 requirement means that those two must be cores. That means that the 3:14 must be a core, with the remaining two as prepreg.// However because 2:3 is prepreg, that means that you cannot have a via going 1:3 - because they wouldn't be able to drill it. You couldn't have 14:16 for the same reason. Next, 1:14 is possible, but not at same time as 3:16 as they cross over. \$\endgroup\$
    – Tom Carpenter
    Commented Jan 21, 2019 at 22:30

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