It is unlikely that the analog signals will disturb each other in this design, they will be changing very slowly (no more than 3V/sec). I will want to keep the GPIO outs away from everything since they'll be PWM, but that isn't a strong enough constraint to answer my question.

In your middle paragraph, by "Logical connections," do you mean connections to the internal logic of the chip (what I termed in my question as "connecting to pins that share the same register") or something else?

Yes, that much is clear. My question is more about the arrangement of the pins: for my 8 analog signals for example, should I try really hard to put them all right next to each other (using eg pins 18-25), or should I try hard to keep them far apart, with two on every side of the device?