the CRC logic which i have used to calculate-

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity ethcrc32 is
port (clk: in STD_LOGIC;                    -- Input clock
     rst: in STD_LOGIC;                 -- Asynchronous reset
     en : in STD_LOGIC;             -- Assert to compute calculations
     is_msb: in STD_LOGIC;              -- Assert to indicate the sens of data_in
       data_in: in STD_LOGIC_VECTOR(7 downto 0);        -- Data to compute
     crc_out: out STD_LOGIC_VECTOR (31 downto 0)    -- CRC output
);

end ethcrc32;

architecture nano of ethcrc32 is

-- The Generator polynomial is
--  32   26   23   22   16   12   11   10   8   7   5   4   2   
-- x  + x  + x  + x  + x  + x  + x  + x  + x + x + x + x + x + x + 1
constant GENERATOR : STD_LOGIC_VECTOR := X"04C11DB7";
begin
process (clk,rst) is
    variable crc_buf : STD_LOGIC_VECTOR (31 downto 0):=x"00000000";
begin
    if rst = '1' then   -- reset signals to values
        crc_buf := (others => '0');
    elsif rising_edge(clk) then  -- operate on positive edge
        if (en='1') then
            if is_msb='1' then
                    for I in data_in'reverse_range loop
                        crc_buf := (crc_buf(30 downto 0) & data_in(I)) XOR (GENERATOR AND (0 to 31=>crc_buf(31)));
                    end loop;
            else
                    for I in data_in'reverse_range loop
                        crc_buf := (crc_buf(30 downto 0) & data_in(I)) XOR (GENERATOR AND (0 to 31=>crc_buf(31)));
                    end loop;
            end if;
        end if;
    end if;
    crc_out<=crc_buf;
end process;

end nano;