I have the following block of code -
always @(posedge clk) begin
if (reset)
oe_hold <= 1'b0;
else begin
oe_hold <= 1'b0;
if (oe && (oe_hold | we))
oe_hold <= 1'b1;
end
end
In the above fragment, oe and we are driven using combinational logic. I'd expect that if oe_hold and oe are high, at clock edge 0 and oe goes low at t=1, then oe_hold would go low at t=2, since oe_hold is a register and should take on its input a cycle later.
However, in simulation, oe_hold behaves like a latch. It goes low at the same clock edge as oe. If I drive oe on the negative edge in the testbench, oe_hold goes low on the following clock edge (i.e., the same edge it went low were oe driven on the positive edge).
Can someone explain this behavior and tell me why it occurs?
Thank you.
Update 1: oe is an input to the device under test and is set like so -
@ (posedge clk) begin
oe = 0;
end
Update 2: 
Update 3: iverilog was used as the simulation tool.