Timeline for How to get a FPGA design that will definitely work on actual hardware
Current License: CC BY-SA 3.0
17 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 25, 2020 at 3:09 | answer | added | Light | timeline score: 2 | |
| Sep 18, 2019 at 5:22 | history | edited | Voltage Spike♦ |
edited tags
|
|
| Mar 2, 2016 at 17:07 | comment | added | ironstein | @ThePhoton the problem was with the constraints, for the pin that I was using as an input, neither did I enable pullup, nor did I hook up an external pullup. That is why it did not work. After making the change, the design executed flawlessly. | |
| Mar 2, 2016 at 17:04 | comment | added | The Photon | In comments on your earlier question you shared your code. I don't see any reason this code should fail to synthesize. But you never mentioned constraints. Did you provide a constraint file that properly specifies the clock timing? Even a simple clock period constraint should be adequate for your design. | |
| Mar 2, 2016 at 14:23 | comment | added | Cort Ammon | Worth noting: synthesizes and "definitely works on actual hardware" are different levels of rigor. There are patterns one can follow to make sure it synthesizes. However, when it comes to making it work on actual hardware, with certainty, one must remember the maxim of simulation: "All models are wrong; some are useful." | |
| Mar 2, 2016 at 14:12 | comment | added | user16324 | First step if you're using ISIM is to turn on the damn range checks. Why they are off by default is anybody's guess but it cost this guy hours. electronics.stackexchange.com/questions/153362/… | |
| Mar 2, 2016 at 13:58 | answer | added | Graham | timeline score: 2 | |
| Mar 2, 2016 at 13:54 | history | tweeted | twitter.com/StackElectronix/status/705028447945490432 | ||
| Mar 2, 2016 at 11:51 | comment | added | pjc50 | Quick googling suggests that this is actually missing from ISIM and you have to use Modelsim or some other third party tools. I'm more familiar with the Altera path (which uses Modelsim). | |
| Mar 2, 2016 at 11:40 | answer | added | apalopohapa | timeline score: 5 | |
| Mar 2, 2016 at 11:39 | comment | added | ironstein | @pjc50 that is actually a very good advice. What is the equivalent of this in Xilinx ISE design suite ? | |
| Mar 2, 2016 at 10:29 | comment | added | pjc50 | You have a testbench or stimulus driving the simulation. Coverage tools tell you how much of the design is actually being exercised by the test, as a percentage. If this number is too low then your testbench is inadequate and you're not testing some cases which could come up in real usage. | |
| Mar 2, 2016 at 9:56 | comment | added | ironstein | @pjc50 I don't understand the question. What do you mean "high level of coverage in simulation" ? | |
| Mar 2, 2016 at 9:55 | comment | added | pjc50 | What sort of problems are you encountering with synthesis? Do you achieve a high level of coverage in the simulation? | |
| Mar 2, 2016 at 6:58 | answer | added | Voltage Spike♦ | timeline score: 15 | |
| Mar 2, 2016 at 5:49 | answer | added | alex.forencich | timeline score: 6 | |
| Mar 2, 2016 at 4:44 | history | asked | ironstein | CC BY-SA 3.0 |