Timeline for shift register problem in VHDL
Current License: CC BY-SA 3.0
10 events
| when toggle format | what | by | license | comment | |
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| Apr 7, 2016 at 14:18 | vote | accept | EEEidolt | ||
| S Mar 16, 2016 at 9:02 | history | suggested | Martin Zabel | CC BY-SA 3.0 |
added viable information from comments
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| Mar 16, 2016 at 8:46 | review | Suggested edits | |||
| S Mar 16, 2016 at 9:02 | |||||
| Mar 16, 2016 at 5:29 | answer | added | Martin Zabel | timeline score: 4 | |
| Mar 16, 2016 at 2:37 | comment | added | EEEidolt | @DaveTweed That's signed(7 downto 0) but how can I change the signal type in a individual process. The signal temp_byte is also been used in other processes so I don't know how to deal with it. | |
| Mar 16, 2016 at 2:32 | comment | added | Dave Tweed |
What about temp_byte?
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| Mar 16, 2016 at 2:21 | comment | added | Dave Tweed | We need to see the declarations for the various signals. Obviously, you missed a type conversion somewhere along the way. | |
| Mar 16, 2016 at 2:20 | history | edited | Dave Tweed | CC BY-SA 3.0 |
fix formatting
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| Mar 16, 2016 at 2:09 | history | edited | EEEidolt | CC BY-SA 3.0 |
added 187 characters in body
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| Mar 16, 2016 at 2:00 | history | asked | EEEidolt | CC BY-SA 3.0 |