Timeline for What is a "half latch" in an FPGA?
Current License: CC BY-SA 3.0
14 events
| when toggle format | what | by | license | comment | |
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| Jan 27, 2018 at 12:16 | comment | added | Dmitry Grigoryev | @damage Exactly. | |
| Jan 27, 2018 at 11:21 | comment | added | andrsmllr | @Dimitry: Nice answer. Do I understand correctly, that half latches are (commonly?) used in FPGA interconnect matrices? And by sourcing constant from "within" the interconnect matrices no logic resources must be used. | |
| Jan 27, 2018 at 11:10 | vote | accept | andrsmllr | ||
| Jan 27, 2018 at 0:13 | comment | added | hmakholm left over Monica | (At first your description sounded to me like the input was supposed to be something like a tri-state common line where some of the time nobody might be driving it). | |
| Jan 27, 2018 at 0:11 | comment | added | hmakholm left over Monica | Ah, so if I understand you correctly, this is for use in a case where in the design phase you can either connect the input signal (in which case you're supposed to be driving it all the time rather than sometimes tri-stating it), or leave it unconnected entirely, in which case the half-latch supplies a default? | |
| Jan 26, 2018 at 23:47 | comment | added | Dmitry Grigoryev | @HenningMakholm And BTW, if you use a full latch, you still have to drive it once to get it into a predictable state, right? | |
| Jan 26, 2018 at 23:38 | comment | added | Dmitry Grigoryev | @HenningMakholm LUT is an acronym for look-up table. I have added an example. | |
| Jan 26, 2018 at 23:36 | history | edited | Dmitry Grigoryev | CC BY-SA 3.0 |
added 428 characters in body
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| Jan 26, 2018 at 23:07 | comment | added | hmakholm left over Monica | A fully functional latch would only need a single weak NMOS in addition to your diagram to pull the input down when the output is high, right? I don't know what a LUT is -- can you say something in your answer about how "used as constants" works if the only thing it can store reliably is an 1? How are these things used? | |
| Jan 26, 2018 at 23:03 | comment | added | Dmitry Grigoryev | @HenningMakholm Why do you think a half-latches only save a single transistor? AFAIK they are used as constants which otherwise would have to be encoded in LUTs. | |
| Jan 26, 2018 at 21:49 | comment | added | hmakholm left over Monica | That sounds like a significant complication of whichever circuitry supplies the input, just to save a single transistor. If you could write something about why on earth that would be worth it, I think it would improve the answer. | |
| Jan 26, 2018 at 21:37 | comment | added | Dmitry Grigoryev | @HenningMakholm Yes, the FPGA drives all half-latches before each programming cycle. | |
| Jan 25, 2018 at 23:56 | comment | added | hmakholm left over Monica | So you're supposed to drive the input high for a moment before floating it, or you will end up with a metastable state that will eventually but unpredictably flip? | |
| Jan 25, 2018 at 15:56 | history | answered | Dmitry Grigoryev | CC BY-SA 3.0 |