Is it bad practice to route high speed signals (like a SPI bus clocked at 4MHz) through PCB vias?

I've noticed a good bit of noise (+-300mV) on my SPI bus signals with 3.3V levels. The signals traces are only about 5cm long but they go through about 5 vias each on the way to their destination. The board has only 2 layers which is why there are so many vias on these lines.

What kind of noise can I expect (if any) to be introduced by a PCB layer change via?

Is it bad practice to route high speed signals (like a SPI bus clocked at 4MHz) through PCB vias?

I've noticed a good bit of noise (+-300mV) on my SPI bus signals with 3.3V levels. The signals traces are only about 5cm long but they go through about 5 vias each on the way to their destination. The board has only 2 layers which is why there are so many vias on these lines.

What kind of noise can I expect (if any) to be introduced by a PCB layer change via?

Lots of good information in the answers. It's going to be hard to pick only one. Given that a PCB via introduces about 1.2nH of inductance and 0.4pF of capacitance the consensus seems to be that the 5 via's wont affect a 4MHz signal in any significant way.

Is it bad practice to route high speed signals (like a SPI bus clocked at 4MHz) through PCB via's?

I've noticed a good bit of noise (+-300mV) on my SPI bus signals with 3.3V levels. The signals traces are only about 5cm long but they go through about 5 via's each on the way to their destination. The board has only 2 layers which is why there are so many via's on these lines.

What kind of noise can I expect (if any) to be introduced by a PCB layer change via?

Is it bad practice to route high speed signals (like a SPI bus clocked at 4MHz) through PCB vias?

I've noticed a good bit of noise (+-300mV) on my SPI bus signals with 3.3V levels. The signals traces are only about 5cm long but they go through about 5 vias each on the way to their destination. The board has only 2 layers which is why there are so many vias on these lines.

What kind of noise can I expect (if any) to be introduced by a PCB layer change via?