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Is it bad practice to route high speed signals (like a SPI bus clocked at 4MHz) through PCB vias?

I've noticed a good bit of noise (+-300mV) on my SPI bus signals with 3.3V levels. The signals traces are only about 5cm long but they go through about 5 vias each on the way to their destination. The board has only 2 layers which is why there are so many vias on these lines.

What kind of noise can I expect (if any) to be introduced by a PCB layer change via?

Lots of good information in the answers. It's going to be hard to pick only one. Given that a PCB via introduces about 1.2nH of inductance and 0.4pF of capacitance the consensus seems to be that the 5 via's wont affect a 4MHz signal in any significant way.

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  • \$\begingroup\$ If you imagine the side view of a trace through a via, how would you expect that shape to affect the signal? \$\endgroup\$
    – ratchet freak
    Commented Apr 11, 2019 at 16:16
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    \$\begingroup\$ A 4 MHz SPI bus is hardly "high speed" today - you do need to think about signal integrity but sane via usage should not be an issue. You should not need five vias to accomplish a 5cm run - did you let an autorouter run wild? For boards someone asking your question would be making, you probably should be manually routing. The "noise" you are measuring is likely a result of how you are measuring, there probably is some overshoot and ringing, but it's not clear you are measuring that. \$\endgroup\$
    – Chris Stratton
    Commented Apr 11, 2019 at 16:20
  • \$\begingroup\$ With two layer board there typically isn't a solid ground plane so the trace impedance is not constant anyway. Thus vias make little difference. And at least they don't cause (significant amount of) noise. Also 4 MHz is not high speed as mentioned in other comments. \$\endgroup\$
    – TemeV
    Commented Apr 11, 2019 at 16:30
  • \$\begingroup\$ for a start, view each via as 1 nanoHenry inductance in series with a transmission line. Then you can refine this model. \$\endgroup\$
    – analogsystemsrf
    Commented Apr 11, 2019 at 16:43
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    \$\begingroup\$ @ChrisStratton I agree with you that 4MHz isn't high speed as high speed comes these days. For the sake of completeness, many signal integrity issues are driven by raise time, rather than fundamental frequency. A 4MHz clock may have a 20ns raise time. \$\endgroup\$
    – Nick Alexeev
    Commented Apr 11, 2019 at 23:50

4 Answers 4

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300mV is a lot for a 3.3V bus. Vias will not cause a problem as a via only adds a few nH of inductance and if the capacitance on either end is lower than 100pF and a trace that short would be under 0.1Ω which would make an RLC resonator at around 1GHz, and you won't see it.

Transmission line effects don't become noticeable until 50MHz, so 4Mhz should be fine.

The most common problem on two layer boards is common mode noise from improper grounding (daisy chaining grounds) and common mode noise. So I would first look at the grounding system in the design, make sure that currents don't create common mode noise through small traces that are daisy chained.

The other problem might be with grounding and where the scope ground is placed.

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  • \$\begingroup\$ The SPI bus is going through a TXB0108 level shifter (5 to 3.3V) so I was expecting the 3.3V signals to be pretty clean. The noise I was seeing was apparently due to how I had the scope connected to the bus. The SPI bus has 3 devices on it, two within 2 cm of the level translator and one about 5cm distance. The furthest device is socketed so I removed it to use the socket pins to attach the scope. With the 3rd device removed the signals had significant noise. I re-measured with the 3rd device attached and the noise was significantly less. \$\endgroup\$
    – Jeff Wahaus
    Commented Apr 12, 2019 at 15:57
  • \$\begingroup\$ Grounding for scopes can be a big problem, if you go faster than 30MHz+ the grounding wire inductance of the probe starts to become noticeable and you need to take steps to make it as short as possible. \$\endgroup\$
    – Voltage Spike ♦
    Commented Apr 12, 2019 at 16:08
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I'm a novice when it comes to higher speed signals, but it just so happens I was researching signal integrity when you asked the question. One source I am referencing is Right the First Time by Lee Ritchey. You will want to check out chapter 25, Right Angle Bends and Vias: Potential Sources of Reflections and Other Problems.

I don't believe the vias will cause any problems in your design. Here is an excerpt from the source:

Vias, when used in traces, are capacitive, not inductive. The capacitance value of a via is small compared to the capacitance of a trace (3.5pF/inch for 50Ω). In general, vias are not visible to signals with edge rates slower than 0.3 ns.

The chapter goes on to discuss reflections due to PCB layer impedance mismatches, however this appears to be a case when manufacturing tolerances are not met.

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  • \$\begingroup\$ I see a reference to Lee Ritchey, I upvote. \$\endgroup\$
    – pfabri
    Commented Aug 29, 2021 at 18:34
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The issue is not the SPI clock being too high frequency (4 MHz). It could be 0.1 Hz and the signal edges would still ring, as it's the edge rate that defines the bandwidth. Typically microcontroller IO pins are moderately strong, and can drive for example a 30pF capacitive load with 4ns rise time or 10pF capacitive load with 2.5nS rise time. That's strong enough to drive 100-120MHz signals out from a MCU, according to STM32F207 datasheet.

What you may be missing is that if your MCU does not have settable pin drive strength, you can slow down the rise/fall times to sane levels by putting for example 33 ohms series terminating resistors at the device that is driving the pins. This way the edges need less bandwidth and there is less ringing. 4MHz SPI running for 5cm of length should not be an issue, but do check what rise/fall times your chips need to work.

Another issue is that your oscilloscope might show ringing for signals just because the scope or probes have 100MHz BW limit and signal edges are fast enough to go over 100MHz BW limit.

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  • \$\begingroup\$ The edge rate that I've measured is around 300ns. There is a good bit of ringing on the MOSI line present but it's gone by the time the rising clock edge happens. I could probably get away with an 8MHz bus clock but not any faster without the ringing becoming an issue. \$\endgroup\$
    – Jeff Wahaus
    Commented Apr 13, 2019 at 0:08
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5MHz is slow. But the bandwidth of the signal depends on risetime.

BW=0.35/Tr so it is 10ns=0.01us the BW= 0.35/0.01us = 35MHz

But if the signal was HDMI or CML logic or even just 1ns risetime, then ;

BW= 350MHz Then we have two Rules of Thumb more maximum path length to ignore reflections from vias or long traces;

1: 1/10 Lambda the 1ns rise time is using v=c/sqrt(Er)
- max path length is 8.5 cm

  1. Slewrate /4
    • max path length is 4.5 cm

For better analysis use some calc tools like Saturn PCB.exe or analysis tools using the ESL,ESR,C(pf) of your via inductance and capacitance into a model to see the result using the VOl/Iol=Ron driver impedance.

Then model into your favorite simulator. Mine is Falstad's

Your results are ONLY as good as your model values as FALSTAD uses ideal voltage sources and wires are ideal. So you add R,L,C values to suit your model.

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