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user4434
user4434
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What is the difference between these statements in VHDL:

  1. if (clk'event and clk='1') then
  2. if rising_edge(clk) then

Are they equivalent ? Do you produce the same behavior (outputs) ? Why would one be used versus the other ?

Also is one synthesizable versus the other ? Which is better for synthesis correct coding ?

What is the difference between these statements in VHDL:

  1. if (clk'event and clk='1') then
  2. if rising_edge(clk) then

Are they equivalent ? Do you produce the same behavior (outputs) ? Why would one be used versus the other ?

What is the difference between these statements in VHDL:

  1. if (clk'event and clk='1') then
  2. if rising_edge(clk) then

Are they equivalent ? Do you produce the same behavior (outputs) ? Why would one be used versus the other ?

Also is one synthesizable versus the other ? Which is better for synthesis correct coding ?

Source Link
user4434
user4434
  • 159
  • 2
  • 13

VHDL Clock Question

What is the difference between these statements in VHDL:

  1. if (clk'event and clk='1') then
  2. if rising_edge(clk) then

Are they equivalent ? Do you produce the same behavior (outputs) ? Why would one be used versus the other ?