Timeline for Do more logic gates in series mean more slowing of the output result?
Current License: CC BY-SA 4.0
14 events
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| Jul 29, 2021 at 14:54 | history | edited | Null♦ | CC BY-SA 4.0 |
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| Jul 29, 2021 at 8:24 | history | edited | Shashank V M |
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| Jul 29, 2021 at 8:11 | history | edited | Shashank V M | CC BY-SA 4.0 |
Edited title, added relevant tags
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| Jul 28, 2021 at 13:14 | vote | accept | Muhammad Ikhwan Perwira | ||
| Jul 28, 2021 at 8:33 | history | edited | JRE | CC BY-SA 4.0 |
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| Jul 28, 2021 at 8:30 | comment | added | Transistor | If you need to add more information then please use the edit link below your question rather than post it as a comment which may be missed. | |
| Jul 28, 2021 at 8:14 | answer | added | Lorenzo Marcantonio | timeline score: 4 | |
| Jul 27, 2021 at 20:49 | review | Close votes | |||
| Jul 29, 2021 at 14:54 | |||||
| Jul 27, 2021 at 20:30 | answer | added | Matt | timeline score: 4 | |
| Jul 27, 2021 at 20:20 | history | edited | Muhammad Ikhwan Perwira | CC BY-SA 4.0 |
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| Jul 27, 2021 at 20:20 | comment | added | user16324 | Unless you use faster gates to compensate for the longer chain of gates. | |
| Jul 27, 2021 at 20:18 | comment | added | Muhammad Ikhwan Perwira |
I was edited my question, in some case there's a way that we can compress the logic gates. Like that De Morgan Law cases, if there's an operation NOT(NOT(A) OR NOT(B)), it can be compressed with A AND B. Both operation give same result, but if only using AND gate it will make operation faster
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| Jul 27, 2021 at 20:17 | history | edited | Muhammad Ikhwan Perwira | CC BY-SA 4.0 |
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| Jul 27, 2021 at 20:08 | history | asked | Muhammad Ikhwan Perwira | CC BY-SA 4.0 |